Sung Kyu Lim

Q: What Schools Are Affiliated With Sung Kyu Lim

Sung Kyu Lim is affiliated with the following schools: California Institute of Technology, Georgia Tech

Sung Kyu Lim's AcademicInfluence.com Rankings

Sung Kyu Lim

Engineering

#7235

World Rank

#8599

Historical Rank

Electrical Engineering

#2242

World Rank

#2348

Historical Rank

Applied Physics

#2461

World Rank

#2502

Historical Rank

engineering Degrees

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Engineering

Sung Kyu Lim's Degrees

PhD Electrical Engineering Stanford University
Masters Electrical Engineering Stanford University
Bachelors Electrical Engineering Seoul National University

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Sung Kyu Lim's Published Works

Number of citations in a given year to any of this author's works

Total number of citations to an author for the works they published in a given year. This highlights publication of the most important work(s) by the author

Published Works

A study of Through-Silicon-Via impact on the 3D stacked IC layout (2009) (211)
3D-MAPS: 3D Massively parallel processor with stacked memory (2012) (176)
TSV stress aware timing analysis with applications to 3D-IC layout optimization (2010) (116)
TSV stress-aware full-chip mechanical reliability analysis and optimization for 3D IC (2014) (110)
Design and CAD methodologies for low power gate-level monolithic 3D ICs (2014) (104)
Thermal Characterization of Interlayer Microfluidic Cooling of Three-Dimensional Integrated Circuits With Nonuniform Heat Flux (2010) (101)
Physical design for 3D system on package (2005) (96)
Stress-driven 3D-IC placement with TSV keep-out zone and regularity study (2010) (96)
Multiobjective Microarchitectural Floorplanning for 2-D and 3-D ICs (2007) (96)
Full-chip TSV-to-TSV coupling analysis and optimization in 3D IC (2011) (92)
3D Floorplanning with Thermal Vias (2006) (89)
Edge separability-based circuit clustering with application to multilevel circuit partitioning (2004) (88)
Study of Through-Silicon-Via Impact on the 3-D Stacked IC Layout (2013) (88)
TSV Stress-Aware Full-Chip Mechanical Reliability Analysis and Optimization for 3-D IC (2011) (86)
Multiway partitioning with pairwise movement (1998) (84)
Large scale circuit partitioning with loose/stable net removal and signal flow based clustering (1997) (81)
Fast and Accurate Analytical Modeling of Through-Silicon-Via Capacitive Coupling (2011) (80)
Low-Power and Reliable Clock Network Design for Through-Silicon Via (TSV) Based 3D ICs (2011) (80)
Edge separability based circuit clustering with application to circuit partitioning (2000) (79)
A design tradeoff study with monolithic 3D integration (2012) (78)
Through-silicon-via management during 3D physical design: When to add and how many? (2010) (77)
Through-silicon-via aware interconnect prediction and optimization for 3D stacked ICs (2009) (75)
Design and analysis of 3D-MAPS: A many-core 3D processor with stacked memory (2010) (75)
Buffered clock tree synthesis for 3D ICs under thermal variations (2008) (70)
Multi-layer floorplanning for reliable system-on-package (2004) (69)
Profile-guided microarchitectural floor planning for deep submicron processor design (2004) (68)
Design method and test structure to characterize and repair TSV defect induced signal degradation in 3D system (2010) (67)
Pre-bond testable low-power clock tree design for 3D stacked ICs (2009) (66)
TSV-aware interconnect length and power prediction for 3D stacked ICs (2009) (63)
Power benefit study for ultra-high density transistor-level monolithic 3D ICs (2013) (63)
Power-performance study of block-level monolithic 3D-ICs considering inter-tier performance variations (2014) (62)
Physical planning with retiming (2000) (62)
Design and Analysis of 3D-MAPS (3D Massively Parallel Processor with Stacked Memory) (2015) (61)
Modeling of electromigration in through-silicon-via based 3D IC (2011) (60)
Placement-Driven Partitioning for Congestion Mitigation in Monolithic 3D IC Designs (2014) (58)
Through-silicon-via-aware delay and power prediction model for buffered interconnects in 3D ICs (2010) (58)
Pre-Bond and Post-Bond Test and Signal Recovery Structure to Characterize and Repair TSV Defect Induced Signal Degradation in 3-D System (2011) (56)
Ultra high density logic designs using transistor-level monolithic 3D integration (2012) (51)
High-density integration of functional modules using monolithic 3D-IC technology (2013) (51)
Ultra-high I/O density glass/silicon interposers for high bandwidth smart mobile applications (2011) (50)
Electromigration modeling and full-chip reliability analysis for BEOL interconnect in TSV-based 3D ICs (2011) (49)
Performance driven multi-level and multiway partitioning with retiming (2000) (49)
Fast and accurate thermal modeling and optimization for monolithic 3D ICs (2014) (49)
Wire congestion and thermal aware 3D global placement (2005) (44)
Monolithic 3D IC vs. TSV-based 3D IC in 14nm FinFET technology (2016) (43)
Shrunk-2-D: A Physical Design Methodology to Build Commercial-Quality Monolithic 3-D ICs (2017) (42)
Design challenges and solutions for ultra-high-density monolithic 3D ICs (2014) (42)
Cascade2D: A design-aware partitioning approach to monolithic 3D IC with 2D commercial tools (2016) (40)
Power and slew-aware clock network design for through-silicon-via (TSV) based 3D ICs (2010) (40)
Placement for large-scale floating-gate field-programable analog arrays (2006) (39)
Full-chip through-silicon-via interfacial crack analysis and optimization for 3D IC (2011) (39)
Design for High Performance, Low Power, and Reliable 3D Integrated Circuits (2012) (39)
A study of IR-drop noise issues in 3D ICs with through-silicon-vias (2010) (39)
VLSI Placement Parameter Optimization using Deep Reinforcement Learning (2020) (39)
Reliable 3-D Clock-Tree Synthesis Considering Nonlinear Capacitive TSV Model With Electrical–Thermal–Mechanical Coupling (2013) (36)
Analysis of TSV-to-TSV coupling with high-impedance termination in 3D ICs (2011) (36)
Co-design of signal, power, and thermal distribution networks for 3D ICs (2009) (35)
Distributed TSV Topology for 3-D Power-Supply Networks (2012) (35)
Power delivery system architecture for many-tier 3D systems (2010) (35)
Ultrahigh Density Logic Designs Using Monolithic 3-D Integration (2013) (34)
FAFNIR: Accelerating Sparse Gathering by Using Efficient Near-Memory Intelligent Reduction (2021) (34)
Low-Power Clock Tree Design for Pre-Bond Testing of 3-D Stacked ICs (2011) (33)
Decoupling-Capacitor Planning and Sizing for Noise and Leakage Reduction (2006) (33)
Ultra-high density 3D SRAM cell designs for monolithic 3D integration (2012) (33)
Full-chip multiple TSV-to-TSV coupling extraction and optimization in 3D ICs (2013) (33)
TSV-Aware Interconnect Distribution Models for Prediction of Delay and Power Consumption of 3-D Stacked ICs (2014) (33)
Design for manufacturability and reliability for TSV-based 3D ICs (2012) (33)
Thermal-aware steiner routing for 3D stacked ICs (2007) (32)
GAN-CTS: A Generative Adversarial Framework for Clock Tree Prediction and Optimization (2019) (32)
Compact-2D: A Physical Design Methodology to Build Commercial-Quality Face-to-Face-Bonded 3D ICs (2018) (32)
Practical Problems in VLSI Physical Design Automation (2008) (32)
A study of stacking limit and scaling in 3D ICs: an interconnect perspective (2009) (32)
Block-level 3D IC design with through-silicon-via planning (2012) (32)
Multi-functional interconnect co-optimization for fast and reliable 3D stacked ICs (2009) (31)
Architecture, Chip, and Package Co-design Flow for 2.5D IC Design Enabling Heterogeneous IP Reuse (2019) (31)
Automatic cell placement for quantum-dot cellular automata (2004) (31)
TSV-Based 3-D ICs: Design Methods and Tools (2017) (30)
Silicon Effect-Aware Full-Chip Extraction and Mitigation of TSV-to-TSV Coupling (2014) (30)
On enhancing power benefits in 3D ICs: Block folding and bonding styles perspective (2014) (29)
Full chip impact study of power delivery network designs in monolithic 3D ICs (2014) (28)
Co-Optimization of signal, power, and thermal distribution networks for 3D ICs (2008) (28)
Backend low-k TDDB chip reliability simulator (2011) (28)
Timing analysis and optimization for 3D stacked multi-core microprocessors (2010) (27)
Performance and Thermal-Aware Steiner Routing for 3-D Stacked ICs (2009) (27)
Robust Clock Tree Synthesis with timing yield optimization for 3D-ICs (2011) (27)
3D module placement for congestion and power noise reduction (2005) (26)
Design automation and testing of monolithic 3D ICs: Opportunities, challenges, and solutions: (Invited paper) (2017) (26)
Placement and Routing for 3-D System-On-Package Designs (2006) (26)
A 14nm FinFET transistor-level 3D partitioning design to enable high-performance and low-cost monolithic 3D IC (2016) (26)
Transient modeling of TSV-wire electromigration and lifetime analysis of power distribution network for 3D ICs (2013) (26)
Thermal-aware 3D Microarchitectural Floorplanning (2004) (25)
TP-GNN: A Graph Neural Network Framework for Tier Partitioning in Monolithic 3D ICs (2020) (25)
Shortest Path and Neighborhood Subgraph Extraction on a Spiking Memristive Neuromorphic Implementation (2019) (24)
Impact of nano-scale through-silicon vias on the quality of today and future 3D IC designs (2011) (24)
Thermal-reliable 3D clock-tree synthesis considering nonlinear electrical-thermal-coupled TSV model (2013) (24)
QCA channel routing with wire crossing minimization (2005) (23)
Signal integrity analysis and optimization for 3D ICs (2011) (23)
Rapid Prototyping of Large-scale Analog Circuits With Field Programmable Analog Array (2007) (23)
Partitioning and placement for buildable QCA circuits (2005) (22)
Performance driven multiway partitioning (2000) (22)
Power, performance, and cost comparisons of monolithic 3D ICs and TSV-based 3D ICs (2015) (22)
Routing optimization of multi-modal interconnects in 3D ICs (2009) (21)
Methodology to determine the impact of linewidth variation on chip scale copper/low-k backend dielectric breakdown (2010) (21)
Power benefit study of monolithic 3D IC at the 7nm technology node (2015) (20)
How to reduce power in 3D IC designs: A case study with OpenSPARC T2 core (2013) (20)
Co-Optimization and Analysis of Signal, Power, and Thermal Interconnects in 3-D ICs (2011) (20)
Electrical Coupling of Monolithic 3-D Inverters (2016) (20)
Node duplication and routing algorithms for quantum-dot cellular automata circuits (2006) (20)
Thermal optimization in multi-granularity multi-core floorplanning (2009) (19)
Full chip power benefits with negative capacitance FETs (2017) (19)
A Floorplan-Aware Dynamic Inductive Noise Controller for Reliable Processor Design (2006) (19)
Designing 3D test wrappers for pre-bond and post-bond test of 3D embedded cores (2011) (19)
Multi-way partitioning using bi-partition heuristics (2000) (19)
Microarchitectural Floorplanning Under Performance and Thermal Tradeoff (2006) (19)
Scan Test of Die Logic in 3-D ICs Using TSV Probing (2015) (19)
Chip/package co-analysis of thermo-mechanical stress and reliability in TSV-based 3D ICs (2012) (19)
Impact of Mechanical Stress on the Full Chip Timing for Through-Silicon-Via-based 3-D ICs (2013) (18)
Slew-aware buffer insertion for through-silicon-via-based 3D ICs (2012) (18)
Noise-Direct: A Technique for Power Supply Noise Aware Floorplanning Using Microarchitecture Profiling (2007) (18)
Exploiting Die-to-Die Thermal Coupling in 3-D IC Placement (2014) (18)
Design Quality Trade-Off Studies for 3-D ICs Built With Sub-Micron TSVs and Future Devices (2012) (18)
Block-level 3-D Global Routing With an Application to 3-D Packaging (2006) (18)
IsoNet: Hardware-Based Job Queue Management for Many-Core Architectures (2013) (17)
Full-Chip Signal Integrity Analysis and Optimization of 3-D ICs (2016) (17)
Exploiting die-to-die thermal coupling in 3D IC placement (2012) (17)
Physical Design Solutions to Tackle FEOL/BEOL Degradation in Gate-level Monolithic 3D ICs (2016) (17)
Impact of size effects in local interconnects for future technology nodes: A study based on full-chip layouts (2014) (17)
On accurate full-chip extraction and optimization of TSV-to-TSV coupling elements in 3D ICs (2013) (17)
Analysis of DC current crowding in through-silicon-vias and its impact on power integrity in 3D ICs (2012) (17)
A generic reconfigurable array specification and programming environment (GRASPER) (2009) (16)
A fast simulation framework for full-chip thermo-mechanical stress and reliability analysis of through-silicon-via based 3D ICs (2011) (16)
Whitespace redistribution for thermal via insertion in 3D stacked ICs (2007) (16)
A novel TSV topology for many-tier 3D power-delivery networks (2011) (16)
Variation-aware clock network design methodology for ultra-low voltage (ULV) circuits (2011) (16)
Effective thermal via and decoupling capacitor insertion for 3D system-on-package (2006) (16)
Electromigration study for multi-scale power/ground vias in TSV-based 3D ICs (2013) (16)
Adaptive Regression-Based Thermal Modeling and Optimization for Monolithic 3-D ICs (2016) (15)
Pin-3D: A Physical Synthesis and Post-Layout Optimization Flow for Heterogeneous Monolithic 3D ICs (2020) (15)
TSV-Aware 3 D Physical Design Tool Needs for Faster Mainstream Acceptance of 3 D ICs (2010) (15)
Net-Sensitivity-Based Optimization of Large-Scale Field-Programmable Analog Array (FPAA) Placement and Routing (2009) (15)
Architecture, Chip, and Package Codesign Flow for Interposer-Based 2.5-D Chiplet Integration Enabling Heterogeneous IP Reuse (2020) (15)
Tier partitioning strategy to mitigate BEOL degradation and cost issues in monolithic 3D ICs (2016) (15)
Bus-aware microarchitectural floorplanning (2008) (15)
Macro-3D: A Physical Design Methodology for Face-to-Face-Stacked Heterogeneous 3D ICs (2020) (15)
Physical layout automation for system-on-packages (2004) (14)
Match-making for Monolithic 3D IC: Finding the right technology node (2016) (14)
Power-supply-network design in 3D integrated systems (2011) (14)
Multi-Objective Microarchitectural Floorplanning For 2 D And 3 D ICs (2006) (14)
Variation-tolerant and low-power clock network design for 3D ICs (2011) (14)
Electromigration Study for Multiscale Power/Ground Vias in TSV-Based 3-D ICs (2014) (14)
TSV Stress-Aware ATPG for 3D Stacked ICs (2012) (14)
Analysis and Design of Energy and Slew Aware Subthreshold Clock Systems (2011) (13)
Research Needs for TSV-Based 3D IC Architectural Floorplanning (2014) (13)
Scan test of die logic in 3D ICs using TSV probing (2012) (13)
Optical Routing for 3-D System-On-Package (2007) (13)
Optical Routing for 3D System-On-Package (2006) (13)
Reliability-aware floorplanning for 3D circuits (2005) (13)
Chip/Package Mechanical Stress Impact on 3-D IC Reliability and Mobility Variations (2013) (13)
The Law of Attraction: Affinity-Aware Placement Optimization using Graph Neural Networks (2021) (13)
Scan chain and power delivery network synthesis for pre-bond test of 3D ICs (2011) (13)
Buffered clock tree sizing for skew minimization under power and thermal budgets (2010) (13)
Monolithic 3D IC design: Power, performance, and area impact at 7nm (2016) (12)
Design quality tradeoff studies for 3D ICs built with nano-scale TSVs and devices (2012) (12)
A Spectral Convolutional Net for Co-Optimization of Integrated Voltage Regulators and Embedded Inductors (2019) (12)
Analysis and Modeling of DC Current Crowding for TSV-Based 3-D Connections and Power Integrity (2014) (12)
Thermal and Crosstalk-Aware Physical Design for 3D System-On-Package (2005) (12)
Electromigration-aware routing for 3D ICs with stress-aware EM modeling (2012) (12)
Impact of through-silicon-via scaling on the wirelength distribution of current and future 3D ICs (2011) (12)
Integrated retiming and simultaneous Vdd/Vth scaling for total power minimization (2006) (12)
Compact-2D: A Physical Design Methodology to Build Two-Tier Gate-Level 3-D ICs (2020) (12)
Backend dielectric chip reliability simulator for complex interconnect geometries (2012) (12)
Slew-aware clock tree design for reliable subthreshold circuits (2009) (11)
Retiming-based timing analysis with an application to mincut-based global placement (2004) (11)
Through-silicon-via-induced obstacle-aware clock tree synthesis for 3D ICs (2012) (11)
Design Methodologies for Low-Power 3-D ICs With Advanced Tier Partitioning (2017) (11)
Heterogeneous Mixed-Signal Monolithic 3-D In-Memory Computing Using Resistive RAM (2021) (11)
How much cost reduction justifies the adoption of monolithic 3D ICs at 7nm node? (2016) (11)
Multi-objective module placement for 3-D system-on-package (2006) (10)
Physical Design and CAD Tools for 3-D Integrated Circuits: Challenges and Opportunities (2015) (10)
Traffic: a novel geometric algorithm for fast wire-optimized floorplanning (2006) (10)
Monolithic 3D IC designs for low-power deep neural networks targeting speech recognition (2017) (10)
Entropy Production-Based Full-Chip Fatigue Analysis: From Theory to Mobile Applications (2019) (10)
Design, packaging, and architectural policy co-optimization for DC power integrity in 3D DRAM (2015) (10)
Bringing 3D ICs to Aerospace: Needs for Design Tools and Methodologies (2017) (10)
Impact and Design Guideline of Monolithic 3-D IC at the 7-nm Technology Node (2017) (10)
Frequency and time domain analysis of power delivery network for monolithic 3D ICs (2017) (10)
Co-design of reliable signal and power interconnects in 3D stacked ICs (2009) (10)
Pseudo-3D Approaches for Commercial-Grade RTL-to-GDS Tool Flow Targeting Monolithic 3D ICs (2020) (10)
Thermal analysis and optimization of 2.5-D integrated voltage regulator (2012) (9)
Four-tier Monolithic 3D ICs: Tier Partitioning Methodology and Power Benefit Study (2016) (9)
Layer Assignment for System on Packages (2003) (9)
Heterogeneous 3D Integration for a RISC-V System With STT-MRAM (2020) (9)
A unified methodology for power supply noise reduction in modern microarchitecture design (2008) (9)
Ultralow Power Circuit Design With Subthreshold/Near-Threshold 3-D IC Technologies (2015) (9)
Thermal Characterization of Interlayer Microfluidic Cooling of Three-Dimensional IC With Non-Uniform Heat Flux (2009) (9)
A Novel 3D DRAM Memory Cube Architecture for Space Applications (2018) (9)
RL-Sizer: VLSI Gate Sizing for Timing Optimization using Deep Reinforcement Learning (2021) (9)
Fast delay estimation with buffer insertion for through-silicon-via-based 3D interconnects (2012) (9)
Tier Adaptive Body Biasing: A Post-Silicon Tuning Method to Minimize Clock Skew Variations in 3-D ICs (2013) (9)
Multi-TSV and E-Field Sharing Aware Full-chip Extraction and Mitigation of TSV-to-Wire Coupling (2015) (8)
Evaluating Chip-Level Impact of Cu/Low- $\kappa $ Performance Degradation on Circuit Performance at Future Technology Nodes (2015) (8)
A study of signal integrity issues in through-silicon-via-based 3D ICs (2010) (8)
Net and pin distribution for 3D package global routing (2004) (8)
On GPU bus power reduction with 3D IC technologies (2014) (8)
A study of TSV variation impact on power supply noise (2011) (8)
Tier-partitioning for power delivery vs cooling tradeoff in 3D VLSI for mobile applications (2015) (8)
Tier Degradation of Monolithic 3-D ICs: A Power Performance Study at Different Technology Nodes (2017) (8)
Simultaneous Delay and Power Optimization for Multi-level Partitioning and Floorplanning with Retiming (2003) (7)
A global router for system-on-package targeting layer and crosstalk minimization (2004) (7)
Doomed Run Prediction in Physical Design by Exploiting Sequential Flow and Graph Learning (2021) (7)
A fine-grained co-simulation methodology for IR-drop noise in silicon interposer and TSV-based 3D IC (2011) (7)
Block-level designs of die-to-wafer bonded 3D ICs and their design quality tradeoffs (2013) (7)
Thermal-driven Circuit Partitioning and Floorplanning with Power Optimization (2003) (7)
Backend Dielectric Reliability Full Chip Simulator (2014) (7)
Three-tier 3D ICs for more power reduction: Strategies in CAD, design, and bonding selection (2015) (7)
Parasitic Extraction for Heterogeneous Face-to-Face Bonded 3-D ICs (2017) (7)
Design and Architectural Co-optimization of Monolithic 3D Liquid State Machine-based Neuromorphic Processor (2018) (7)
How to Cope with Slow Transistors in the Top-tier of Monolithic 3D ICs: Design Studies and CAD Solutions (2016) (7)
Fast and accurate full-chip extraction and optimization of TSV-to-wire coupling (2014) (7)
Transistor-level monolithic 3D standard cell layout optimization for full-chip static power integrity (2017) (7)
A Twin Memristor Synapse for Spike Timing Dependent Learning in Neuromorphic Systems (2018) (7)
Backend dielectric reliability simulator for microprocessor system (2012) (7)
Module placement for power supply noise and wire congestion avoidance in 3D packaging (2004) (6)
Statistical Bellman-Ford algorithm with an application to retiming (2006) (6)
A General Framework For VLSI Tool Parameter Optimization with Deep Reinforcement Learning (2020) (6)
Parameter Extraction and Power/Performance Analysis of Monolithic 3-D Inverter (M3INV) (2019) (6)
Wire-driven microarchitectural design space exploration (2005) (6)
VLSI Placement Optimization using Graph Neural Networks (2020) (6)
Full-chip inter-die parasitic extraction in face-to-face-bonded 3D ICs (2015) (6)
Residual Stress and Pop-Out Simulation for TSVs and Contacts in Via-Middle Process (2017) (6)
INVITED: RTL-to-GDS Tool Flow and Design-for-Test Solutions for Monolithic 3D ICs (2019) (6)
A novel geometric algorithm for fast wire-optimized floorplanning (2003) (6)
A Logic-on-Memory Processor-System Design With Monolithic 3-D Technology (2019) (6)
Built-in Self-Test for Inter-Layer Vias in Monolithic 3D ICs (2019) (6)
Snap-3D: A Constrained Placement-Driven Physical Design Methodology for Face-to-Face-Bonded 3D ICs (2021) (6)
Impact of TSV and Device Scaling on the Quality of 3D ICs (2015) (6)
Transition delay fault testing of 3D ICs with IR-drop study (2012) (6)
A Fast Learning-Driven Signoff Power Optimization Framework (2020) (6)
Improving Performance under Process and Voltage Variations in Near-Threshold Computing Using 3D ICs (2017) (6)
Global Placement for Quantum-dot Cellular Automata Based Circuits (2003) (6)
Layer assignment for reliable system-on-package (2004) (6)
Simulation of system backend dielectric reliability (2014) (6)
TSV density-driven global placement for 3D stacked ICs (2011) (6)
Full Chip Impact Study of Power Delivery Network Designs in Gate-Level Monolithic 3-D ICs (2017) (6)
Performance, Power, and Area of Standard Cells in Sub 3 nm Node Using Buried Power Rail (2022) (6)
Design and analysis of 3D IC-based low power stereo matching processors (2013) (6)
Fine-Grained 3-D IC Partitioning Study With a Multicore Processor (2015) (5)
Probe-Pad Placement for Prebond Test of 3-D ICs (2016) (5)
A Floorplan-Aware Dynamic Inductive Noise Controller for Reliable 2D and 3D Microprocessors (2006) (5)
Electrical Coupling and Simulation of Monolithic 3D Logic Circuits and Static Random Access Memory (2019) (5)
Partitioning and placement for buildable QCA circuits (2005) (5)
Breaking Barriers: Maximizing Array Utilization for Compute in-Memory Fabrics (2020) (5)
Design and Analysis of a Stochastic Flash Analog-to-Digital Converter in 3D IC technology for integration with ultrasound transducer array (2016) (5)
Through-silicon-via material property variation impact on full-chip reliability and timing (2014) (5)
TSV array utilization in low-power 3D clock network design (2012) (5)
Road to High-Performance 3D ICs: Performance Optimization Methodologies for Monolithic 3D ICs (2018) (5)
Transient Modeling of Electromigration and Lifetime Analysis of Power Distribution Network for 3 D ICs (2013) (5)
Advances in Design and Test of Monolithic 3-D ICs (2020) (5)
Coupling capacitance in face-to-face (F2F) bonded 3D ICs: Trends and implications (2015) (5)
Thermal-aware 3 D Microarchitectural Floorplanning (2004) (5)
Integrated microarchitectural floorplanning and run-time controller for inductive noise mitigation (2011) (5)
Thermal impact study of block folding and face-to-face bonding in 3D IC (2015) (4)
LCP: A Low-Communication Parallelization Method for Fast Neural Network Inference in Image Recognition (2020) (4)
Worst-Case Eye Analysis of High-Speed Channels Based on Bayesian Optimization (2021) (4)
Impact of irregular geometries on low-k dielectric breakdown (2011) (4)
Power supply noise-aware 3D floorplanning for system-on-package (2005) (4)
Multi-functional Interconnect Co-optimization for Fast and Reliable 3 D Stacked (2009) (4)
Vortex: OpenCL Compatible RISC-V GPGPU (2020) (4)
Simulating and Estimating the Behavior of a Neuromorphic Co-Processor (2017) (4)
Design Flow for Active Interposer-Based 2.5-D ICs and Study of RISC-V Architecture With Secure NoC (2020) (4)
Built-in Self-Test and Fault Localization for Inter-Layer Vias in Monolithic 3D ICs (2022) (4)
Automated I/O Library Generation for Interposer-Based System-in-Package Integration of Multiple Heterogeneous Dies (2020) (4)
Fast Layout Generation of RF Embedded Passive Circuits Using Mathematical Programming (2012) (4)
Security Closure of Physical Layouts ICCAD Special Session Paper (2021) (4)
Global bus route optimization with application to microarchitectural design exploration (2008) (4)
Full-chip monolithic 3D IC design and power performance analysis with ASAP7 library: (Invited Paper) (2017) (4)
Hierarchical placement for large-scale FPAA (2005) (4)
3D IC-package-board co-analysis using 3D EM simulation for mobile applications (2013) (4)
System-Level Power Delivery Network Analysis and Optimization for Monolithic 3-D ICs (2019) (4)
High-Performance Logic-on-Memory Monolithic 3-D IC Designs for Arm Cortex-A Processors (2021) (3)
Impact of die partitioning on reliability and yield of 3D DRAM (2014) (3)
Cross-Domain Optimization of Ferroelectric Parameters for Negative Capacitance Transistors—Part I: Constant Supply Voltage (2020) (3)
Performance driven circuit partitioning (2000) (3)
Exploration of temperature-aware refresh schemes for 3D stacked eDRAM caches (2016) (3)
Introduction to special issue on demonstrable software systems and hardware platforms (2007) (3)
The Impact of 3D Stacking and Technology Scaling on the Power and Area of Stereo Matching Processors (2017) (3)
In-growth test for monolithic 3D integrated SRAM (2018) (3)
More Power Reduction With 3-Tier Logic-on-Logic 3-D ICs (2016) (3)
Wire Congestion And Thermal Aware Global Placement For 3D VLSI Circuits (2004) (3)
Low Power Monolithic 3D IC Design of Asynchronous AES Core (2015) (3)
Mapping algorithm for large-scale field programmable analog array (2005) (3)
Power, Performance, and Area Benefit of Monolithic 3D ICs for On-Chip Deep Neural Networks Targeting Speech Recognition (2018) (3)
Pin-in-the-middle: an efficient block pin assignment methodology for block-level monolithic 3D ICs (2020) (3)
Novel crack sensor for TSV-based 3D integrated circuits: Design and deployment perspectives (2013) (3)
Regular Versus Irregular TSV Placement for 3D IC (2013) (3)
3D IC power benefit study under practical design considerations (2015) (3)
Chip/package co-analysis and inductance extraction for fan-out wafer-level-packaging (2017) (3)
Design Challenges and Solutions for Monolithic 3D ICs (2017) (2)
Evaluating online-learning in memristive neuromorphic circuits (2017) (2)
Stacking integration methodologies in 3D IC for 3D ultrasound image processing application: A stochastic flash ADC design case study (2015) (2)
Performance-driven global placement via adaptive network characterization (2004) (2)
ML-Based Wire RC Prediction in Monolithic 3D ICs with an Application to Full-Chip Optimization (2021) (2)
Opportunities and Challenges in SRAM Design with Monolithic 3 D Technology (2011) (2)
Die-to-Die Parasitic Extraction Targeting Face-to-Face Bonded 3D ICs (2015) (2)
Automatic Placement for Quantum Cell Automata (2003) (2)
Driving Early Physical Synthesis Exploration through End-of-Flow Total Power Prediction (2022) (2)
Placement Optimization via PPA-Directed Graph Clustering (2022) (2)
Improving performance in near-threshold circuits using 3D IC technology (2015) (2)
Profile-Driven Instruction Mapping for Dataflow Architectures (2006) (2)
Decoupling capacitor planning with analytical delay model on RLC power grid (2009) (2)
MemPool-3D: Boosting Performance and Efficiency of Shared-L1 Memory Many-Core Clusters with 3D Integration (2021) (2)
Power, Performance, Area and Cost Analysis of Memory-on-Logic Face-to-Face Bonded 3D Processor Designs (2021) (2)
Design Automation and Test Solutions for Monolithic 3D ICs (2022) (2)
Power Supply Noise-Aware Scan Test Pattern Reshaping for At-Speed Delay Fault Testing of Monolithic 3D ICs * (2020) (2)
Design and Test of 3 D-MAPS , a 3 D Die-Stack Many-Core Processor (2010) (2)
RTL-to-GDS Design Tools for Monolithic 3D ICs (2020) (2)
Simultaneous delay and power optimization in global placement (2004) (2)
Power Delivery and Thermal-Aware Arm-Based Multi-Tier 3D Architecture (2021) (2)
Design and analysis of ultra low power processors using sub/near-threshold 3D stacked ICs (2013) (2)
Placement for configurable dataflow architecture (2005) (2)
FLASHRAD: A Reliable 3D Rad Hard Flash Memory Cube Utilizing COTS for Space (2019) (2)
A COTS-Based Novel 3-D DRAM Memory Cube Architecture for Space Applications (2020) (2)
Silicon vs. Organic Interposer: PPA and Reliability Tradeoffs in Heterogeneous 2.5D Chiplet Integration (2020) (2)
Optimal Ferroelectric Parameters for Negative Capacitance Field-Effect Transistors Based on Full-Chip Implementations—Part II: Scaling of the Supply Voltage (2020) (2)
Full-Chip Electro-Thermal Coupling Extraction and Analysis for Face-to-Face Bonded 3D ICs (2020) (2)
Layer Assignment for System-on-Package (2003) (2)
Bringing 3D COTS DRAM Memory Cubes to Space (2019) (2)
Hier-3D: A Hierarchical Physical Design Methodology for Face-to-Face-Bonded 3D ICs (2022) (2)
Monolithic 3D Inverter with Interface Charge: Parameter Extraction and Circuit Simulation (2021) (1)
Reliability and performance-aware 3D SRAM design (2011) (1)
Chain-Based Approach for Fast Through-Silicon-Via Coupling Delay Estimation (2017) (1)
Design-Aware Partitioning-Based 3-D IC Design Flow With 2-D Commercial Tools (2022) (1)
ART-3D: Analytical 3D Placement with Reinforced Parameter Tuning for Monolithic 3D ICs (2022) (1)
Micro-bumping, Hybrid Bonding, or Monolithic? A PPA Study for Heterogeneous 3D IC Options (2021) (1)
Reducing Compilation Effort in Commercial FPGA Emulation Systems Using Machine Learning (2019) (1)
Device Coupling Effects of Monolithic 3D Inverters (2016) (1)
Die-to-package coupling extraction for fan-out wafer-level-packaging (2017) (1)
Heterogeneous 3D ICs: Current Status and Future Directions for Physical Design Technologies (2021) (1)
Interdie Coupling Extraction and Physical Design Optimization for Face-to-Face 3-D ICs (2018) (1)
Logic Monolithic 3D ICs: PPA Benefits and EDA Tools Necessary (2019) (1)
Ultra low power 2-tier 3D stacked sub-threshold H.264 intra frame encoder (2013) (1)
Timing Analysis and Optimization for Many-Tier 3 D ICs (2010) (1)
ILP-based Supply and Threshold Voltage Assignment For Total Power Minimization (2007) (1)
POWER SUPPLY NOISE ANALYSIS FOR 3 D ICS USING THROUGH-SILICON-VIAS (2010) (1)
A Fault-Tolerant and High-Speed Memory Controller Targeting 3D Flash Memory Cubes for Space Applications (2020) (1)
Test-TSV estimation during 3D-IC partitioning (2013) (1)
Microarchitecture-aware physical planning for deep submicron technology (2006) (1)
Modeling and Benchmarking Back End Of The Line Technologies on Circuit Designs at Advanced Nodes (2020) (1)
TSV-to-TSV Coupling Analysis and Optimization (2013) (1)
Global Routing Paradigm for System-on-Package (2003) (1)
Congestion and Power Integrity Aware Placement and Routing for 3D Packaging (2004) (1)
TDDB chip reliability in copper interconnects (2010) (1)
Tier Partitioning and Flip-flop Relocation Methods for Clock Trees in Monolithic 3D ICs (2019) (1)
On diagnosable and tunable 3D clock network design for lifetime reliability enhancement (2015) (1)
Monolithic 3D Compute-in-Memory Accelerator with BEOL Transistor based Reconfigurable Interconnect (2021) (1)
On Advancing Physical Design using Graph Neural Networks (Invited Paper) (2022) (1)
Fast bidirectional shortest path on GPU (2016) (1)
Pseudo-3D Physical Design Flow for Monolithic 3D ICs: Comparisons and Enhancements (2021) (1)
A ReRAM Memory Compiler for Monolithic 3D Integrated Circuits in a Carbon Nanotube Process (2022) (1)
Global Routing for Three Dimensional Packaging (2003) (1)
Low Power Clock Routing for 3D IC (2013) (1)
A Compute-in-Memory Hardware Accelerator Design With Back-End-of-Line (BEOL) Transistor Based Reconfigurable Interconnect (2022) (1)
Chiplet/Interposer Co-Design for Power Delivery Network Optimization in Heterogeneous 2.5-D ICs (2021) (1)
Machine Learning Based Variation Modeling and Optimization for 3D ICs (2016) (1)
Enabling 3 D Integration Through Optimal Topography (2010) (1)
Improving FPGA-Based Logic Emulation Systems through Machine Learning (2020) (1)
Impact of Multi-level Clustering on Performance Driven Global Placement (2003) (0)
Channel and Pin Assignment for Three Dimensional Packaging Routing (2004) (0)
A Study on the Impact of Nano-Scale TSVs on 3 D IC Designs (2011) (0)
3D IC Cooling with Micro-Fluidic Channels (2013) (0)
Multi-Net Routing (2008) (0)
ECO-GNN: Signoff Power Prediction using Graph Neural Networks with Subgraph Approximation (2022) (0)
3D IC Tier Partitioning of Memory Macros: PPA vs. Thermal Tradeoffs (2022) (0)
Hot Chips 2020 Posters (2020) (0)
Needs for TSV-Based 3 D IC Architectural Floorplanning (2014) (0)
Physical Design Challenges and Solutions for Emerging Heterogeneous 3D Integration Technologies (2021) (0)
Metal Layer Sharing: A Routing Optimization Technique for Monolithic 3D ICs (2022) (0)
Power Delivery Network Design for 3D IC (2013) (0)
3D Clock Routing for Pre-bond Testability (2013) (0)
Title Thermal-reliable 3 D clock-tree synthesis consideringnonlinear electrical-thermal-coupled TSV model (2019) (0)
Machine Learning Integrated Pseudo-3-D Flow for Monolithic 3-D ICs (2021) (0)
Research and Teaching Statement 1.1.1 Improved Iterative Methods (2007) (0)
GNN-Based Multi-Bit Flip-Flop Clustering and Post-Clustering Design Optimization for Energy-Efficient 3D ICs (2023) (0)
Runtime memory optimization and GPU / manycore architectures (2017) (0)
Power Supply Noise-Aware At-Speed Delay Fault Testing of Monolithic 3-D ICs (2021) (0)
Parameter Optimization of VLSI Placement Through Deep Reinforcement Learning (2023) (0)
ParaMitE: Mitigating Parasitic CNFETs in the Presence of Unetched CNTs (2021) (0)
3D Chip/Package Co-analysis of Stress-Induced Timing Variations (2013) (0)
Buffer Insertion for 3D IC (2013) (0)
Automatic Generation of Translators for Packet-Based and Emerging Protocols (2021) (0)
A Clock Tree Prediction and Optimization Framework Using Generative Adversarial Learning (2021) (0)
Large Scale Circuit Partitioning With Loose/Stable Net Removal And Signal Flow Based Hierarchical Cl (1997) (0)
Preface So I devoted several months in privacy to the composition of a treatise on the mysteries of Three Dimensions (2017) (0)
Thermal-Aware Gate-Level Placement for 3D IC (2013) (0)
An Efficient Computation of Statistically Critical Sequential Paths Under Retiming (2007) (0)
Heterogeneous Monolithic 3D ICs: EDA Solutions, and Power, Performance, Cost Tradeoffs (2021) (0)
Congestion-Driven Global Placement for Three Dimensional VLSI Circuits (2003) (0)
Power, Performance, Area, and Cost Analysis of Face-to-Face-Bonded 3-D ICs (2023) (0)
On Legalization of Die Bonding Bumps and Pads for 3D ICs (2023) (0)
Impact of transistor technology on power savings in monolithic 3D ICs (2016) (0)
Physical Design for 3D ICs (2016) (0)
Snap-3D: A Constrained Placement-Driven Physical Design Methodology for High Performance 3D ICs (2022) (0)
Unsupervised Digit Recognition Using Cosine Similarity In A Neuromemristive Competitive Learning System (2022) (0)
Mechanical Reliability Analysis and Optimization for 3D ICs (2013) (0)
New antioxidants and process for its preparation (2000) (0)
Modeling of Atomic Concentration at the Wire-to-TSV Interface (2013) (0)
Co-optimization of Power, Thermal, and Signal Interconnect for 3D ICs (2011) (0)
3DIC 2019 Conference Organization (2019) (0)
Guest Editors' Introduction: Advances in 3-D Integrated Circuits, Systems, and CAD Tools (2015) (0)
WATERMARKING FPGA BITSTREAM FOR IP PROTECTION (2008) (0)
Ultralow Power Processor Design with 3D IC Operating at Sub/Near-Threshold Voltages (2016) (0)
Parallel VLSI detailed routing using general-purpose computing on graphics processing unit (2012) (0)
Clock Delivery Network Design and Analysis for Interposer-Based 2.5-D Heterogeneous Systems (2021) (0)
Multi-objective Architectural Floorplanning for 3D IC (2013) (0)
3D Interconnect Extraction (2017) (0)
MILP-based placement and routing for dataflow architecture (2005) (0)
DREAM-GAN: Advancing DREAMPlace towards Commercial-Quality using Generative Adversarial Learning (2023) (0)
An SRAM Compiler for Monolithic-3-D Integrated Circuit With Carbon Nanotube Transistors (2021) (0)
Steiner Routing for 3D IC (2013) (0)
Design and CAD Solutions for Cooling and Power Delivery for Monolithic 3D‐ICs (2019) (0)
Session details: Enabling design for resilience (2012) (0)
TCAD SIMULATION FRAMEWORK FOR THE STUDY OF TSV-DEVICE INTERACTION (2013) (0)
Full-Chip Power/Performance Benefits of Carbon Nanotube-Based Circuits (2015) (0)
Power Delivery Solutions and PPA Impacts in Micro-Bump and Hybrid-Bonding 3D ICs (2022) (0)
Physical design automation for system-on-packages and 3d-integrated circuits (2006) (0)
4 Runtime memory optimization and GPU / manycore architectures (2017) (0)
Built-In Self-Test of High-Density and Realistic ILV Layouts in Monolithic 3-D ICs (2023) (0)
A PPA Study of Reinforced Placement Parameter Autotuning: Pseudo-3D vs. True-3D Placers (2023) (0)
Area-efficient and Low-power Face-to-Face-bonded 3D Liquid State Machine Design (2018) (0)
Session details: Smart grids (2012) (0)
Machine Learning Based Variation Modeling and Optimization for 3 D ICs (2016) (0)
Impact of TSV Scaling on 3D IC Design Quality (2013) (0)
Placement and routing of RF embedded passive designs in LCP substrate (2007) (0)
Enabling Technologies Physical Design for 3d System on Package (0)
Routing Layer Sharing: A New Opportunity for Routing Optimization in Monolithic 3D ICs (2022) (0)
An Effective Block Pin Assignment Approach for Block-Level Monolithic 3-D ICs (2021) (0)
TSV Etch 25 o C Liner Deposition TSV Fill (2016) (0)
Statistical Array Allocation and Partitioning for Compute In-Memory Fabrics (2020) (0)
Guest Editors' Introduction: Advances in 3-D Integrated Circuits, Systems, and CAD Tools - Part 2 (2015) (0)
A Machine Learning-Powered Tier Partitioning Methodology for Monolithic 3-D ICs (2022) (0)
TSV Interfacial Crack Analysis and Optimization (2013) (0)
Chip/Package Co-analysis of Mechanical Stress for 3D IC (2013) (0)
Table of Contents: MICRO-39 2006 39 th Annual International Symposium on Microarchitecture (2006) (0)
Impact of Mechanical Stress on Timing Variation for 3D IC (2013) (0)
TSV Current Crowding and Power Integrity (2013) (0)
Automatic Layout Generation of RF Embedded Passive Designs (2007) (0)

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