Sung-mo (steve) Kang
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Sung-mo (steve) Kangengineering Degrees
Engineering
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Electrical Engineering
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#1983
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Engineering
Sung-mo (steve) Kang's Degrees
- PhD Electrical Engineering Stanford University
- Masters Electrical Engineering Stanford University
- Bachelors Electrical Engineering Seoul National University
Why Is Sung-mo (steve) Kang Influential?
(Suggest an Edit or Addition)Sung-mo (steve) Kang's Published Works
Number of citations in a given year to any of this author's works
Total number of citations to an author for the works they published in a given year. This highlights publication of the most important work(s) by the author
Published Works
- CMOS digital integrated circuits (1995) (372)
- Memristor Applications for Programmable Analog ICs (2011) (344)
- An exact solution to the transistor sizing problem for CMOS circuits using convex optimization (1993) (287)
- Compact Models for Memristors Based on Charge-Flux Constitutive Relationships (2010) (228)
- Cell-level placement for improving substrate thermal distribution (2000) (220)
- Coupling-driven signal encoding scheme for low-power interface design (2000) (185)
- A simple rate-equation-based thermal VCSEL model (1999) (159)
- Modeling and simulation of interconnection delays and crosstalks in high-speed integrated circuits (1990) (146)
- ILLIADS-T: an electrothermal timing simulator for temperature-sensitive reliability diagnosis of CMOS VLSI chips (1998) (134)
- A comprehensive circuit-level model of vertical-cavity surface-emitting lasers (1999) (127)
- Low-power small-area ±7.28 ps jitter 1 GHz DLL-based clock generator (2002) (125)
- Development of a wide tuning range MEMS tunable capacitor for wireless communication systems (2000) (124)
- A low-swing clock double-edge triggered flip-flop (2001) (121)
- Worst-case analysis and optimization of VLSI circuit performances (1995) (112)
- Electrothermal Analysis of VLSI Systems (2000) (111)
- iTEM: a temperature-dependent electromigration reliability diagnosis tool (1997) (102)
- Interconnect thermal modeling for accurate simulation of circuittiming and reliability (2000) (102)
- Memristors: Devices, Models, and Applications [Scanning the Issue] (2012) (88)
- CMOS Digital Integrated Circuits: Analysis & Design, 4th Edition (2014) (87)
- Rate-equation-based laser models with a single solution regime (1997) (83)
- Hot-Carrier Reliability Of MOS VLSI Circuits (1993) (78)
- Circuit-level electrothermal simulation of electrical overstress failures in advanced MOS I/O protection devices (1994) (78)
- Reconfigurable Stateful nor Gate for Large-Scale Logic-Array Integrations (2011) (77)
- Statistical Performance Modeling and Parametric Yield Estimation of MOS VLSI (1987) (76)
- Memristor-based fine resolution programmable resistance and its applications (2009) (68)
- A high-performance OC-12/OC-48 queue design prototype for input-buffered ATM switches (1997) (63)
- Low-power small-area /spl plusmn/7.28 ps jitter 1 GHz DLL-based clock generator (2002) (62)
- Fast Timing Simulation Of Transient Faults In Digital Circuits (1994) (62)
- Spatially independent VCSEL models for the simulation of diffusive turn-off transients (1999) (58)
- Self-Adaptive Write Circuit for Low-Power and Variation-Tolerant Memristors (2010) (55)
- A field-programmable analog array (FPAA) using switched-capacitor techniques (1996) (55)
- Field Programmable Stateful Logic Array (2011) (55)
- Temperature-Aware Placement for SOCs (2006) (54)
- An Efficient Approach to Gate Matrix Layout (1987) (53)
- Modeling of nMOS transistors for simulation of hot-carrier-induced device and circuit degradation (1992) (52)
- Transforming Tucker's linearization laser rate equations to a form that has a single solution regime (1995) (52)
- Analysis of Passive Memristive Devices Array: Data-Dependent Statistical Model and Self-Adaptable Sense Resistance for RRAMs (2012) (49)
- BOLTZMANN–ARRHENIUS–ZHURKOV (BAZ) MODEL IN PHYSICS-OF-MATERIALS PROBLEMS (2013) (48)
- 4.2W CMOS Frequency Synthesizer for 2.4GHz ZigBee Application with Fast Settling Time Performance (2006) (47)
- Standard cell placement for even on-chip thermal distribution (1999) (47)
- Convexity-based algorithms for design centering (1993) (47)
- A MODFET-based optoelectronic integrated circuit receiver for optical interconnects (1993) (46)
- iCOACH: a circuit optimization aid for CMOS high-performance circuits (1988) (46)
- Resistive Computing: Memristors-Enabled Signal Multiplication (2013) (45)
- Compact Circuit Model and Hardware Emulation for Floating Memristor Devices (2013) (45)
- Carrier reuse with gain compression and feed-forward semiconductor optical amplifiers (2002) (45)
- Improvements to the standard theory for photoreceiver noise (1994) (44)
- ILLIADS: a fast timing and reliability simulator for digital MOS circuits (1993) (43)
- Modeling of quantum-well lasers for computer-aided analysis of optoelectronic integrated circuits (1990) (43)
- Fringing field effects on electrical resistivity of semiconductor nanowire-metal contacts (2008) (43)
- Circuit-level simulation of CDM-ESD and EOS in submicron MOS devices (1996) (42)
- Skew-tolerant high-speed (STHS) domino logic (2001) (42)
- Power Blurring: Fast Static and Transient Thermal Analysis Method for Packaged Integrated Circuits and Power Devices (2014) (41)
- Analytic transient solution of general MOS circuit primitives (1992) (39)
- Modeling and simulation of hot-carrier-induced device degradation in MOS circuits (1993) (37)
- Chip-level charged-device modeling and simulation in CMOS integrated circuits (2003) (36)
- An accurate analytical delay model for BiCMOS driver circuits (1990) (36)
- An algorithm for automatic model-order reduction of nonlinear MEMS devices (2000) (36)
- A CMOS self-regulating VCO with low supply sensitivity (2004) (36)
- Scalable optoelectronic ATM networks: the iPOINT fully functional testbed (1995) (35)
- RRAM-based TCAMs for pattern search (2016) (34)
- Memristive XOR for resistive multiplier (2012) (33)
- Design Automation for Timing-Driven Layout Synthesis (1992) (33)
- A temperature-aware simulation environment for reliable ULSI chipdesign (2000) (33)
- Modeling of InGaAs MSM photodetector for circuit-level simulation (1996) (33)
- Physical Design for Multichip Modules (1994) (33)
- Fast And Accurate Timing Simulation With Regionwise Quadratic Models Of Mos I-V Characteristics (1994) (33)
- An efficient method for hot-spot identification in ULSI circuits (1999) (32)
- Fast Approximation of the Transient Response of Lossy Transmission Line Trees (1993) (32)
- Detailed layer assignment for MCM routing (1992) (31)
- A global delay model for domino cmos circuits with application to transistor sizing (1990) (31)
- Elements of low power design for integrated systems (2003) (31)
- Computationally efficient simulation of a lossy transmission line with skin effect by using numerical inversion of Laplace transform (1992) (31)
- An analysis of inductive peaking in photoreceiver design (1992) (31)
- Electrical overstress and electrostatic discharge (1995) (31)
- A 2 GHz 130 mW Direct-Digital Frequency Synthesizer With a Nonlinear DAC in 55 nm CMOS (2014) (31)
- A low energy encoding technique for reduction of coupling effects in SoC interconnects (2000) (30)
- Analog Weights in ReRAM DNN Accelerators (2019) (30)
- Modeling of a concentrating photovoltaic system for optimum land use (2013) (29)
- Metal--Metal Matrix (M3) for High-Speed MOS VLSI Layout (1987) (29)
- EOS/ESD protection circuit design for deep submicron SOI technology (1995) (28)
- Statistical estimation of average power dissipation in CMOS VLSI circuits using nonparametric techniques (1996) (28)
- A 32-bit carry lookahead adder using dual-path all-N logic (2005) (28)
- A new design of a fast barrel switch network (1992) (27)
- Theoretical Foundations of Memristor Cellular Nonlinear Networks: A DRM2-Based Method to Design Memcomputers With Dynamic Memristors (2020) (27)
- Statistical Estimation Of Average Power Dissipation In Sequential Circuits (1997) (27)
- Matrix unit cell scheduler (MUCS) for input-buffered ATM switches (1998) (26)
- Electrical overstress (EOS) power profiles: A guideline to qualify EOS hardness of semiconductor devices (1993) (26)
- Transient simulation of lossy coupled transmission lines using iterative linear least square fitting and piecewise recursive convolution (1996) (26)
- A design of CMOS polycell for LSI circuits (1981) (26)
- Computer-Aided Design of Optoelectronic Integrated Circuits and Systems (1996) (25)
- Computer Modeling and Simulation of the Optoelectronic Technology Consortium (OETC) Optical Bus (1997) (25)
- Estimation of maximum transition counts at internal nodes in CMOS VLSI circuits (1995) (25)
- Chip-level simulation for CDM failures in multi-power ICs (2000) (25)
- High-Density Memristor-CMOS Ternary Logic Family (2020) (24)
- EOS/ESD reliability of deep sub-micron NMOS protection devices (1995) (24)
- Method of images for the fast calculation of temperature distributions in packaged VLSI chips (2007) (24)
- Modeling of Electrical Overstress in Integrated Circuits (1994) (24)
- Model-order reduction of nonlinear MEMS devices through arclength-based Karhunen-Loeve decomposition (2001) (23)
- An integrated hot-carrier degradation simulator for VLSI reliability analysis (1990) (23)
- iEDISON: an interactive statistical design tool for MOS VLSI circuits (1988) (23)
- Stateful logic pipeline architecture (2011) (23)
- Tracking control of high‐concentration photovoltaic systems for minimizing power losses (2014) (23)
- Leakage-proof domino circuit design for deep sub-100 nm technologies (2004) (23)
- Transient simulation of heterojunction photodiodes-part I: computational methods (1995) (22)
- Studies of EOS susceptibility in 0.6 μm nMOS ESD I/O protection structures (1994) (21)
- New algorithms for circuit simulation of device breakdown (1992) (21)
- High-performance MCM routing (1993) (21)
- A Switched Capacitor Approach to Field-Programmable Analog Array (FPAA) Design (1998) (20)
- Simulation and modeling: simulating optical interconnects (1995) (20)
- Noise constrained transistor sizing and power optimization for dual Vst domino logic (2002) (20)
- An empirical model for accurate estimation of routing delay in FPGAs (1995) (20)
- A novel method to extract the series resistances of individual cells in a photovoltaic module (2013) (20)
- Probe-based Algorithm for QoS Specification and Adaptation (1996) (20)
- Low power and high performance circuit techniques for high fan-in dynamic gates (2004) (20)
- FAST THERMAL ANALYSIS OF VERTICALLY INTEGRATED CIRCUITS (3-D ICS) USING POWER BLURRING METHOD (2009) (20)
- ETS-A: a new electrothermal simulator for CMOS VLSI circuits (1996) (19)
- Low-power adiabatic computing with NMOS energy recovery logic (2000) (19)
- Circuit Design for Reliability (1993) (19)
- Real-time prioritized call admission control in a base station scheduler (2000) (19)
- Gate Matrix Layout of Random Control Logic in a 32-bit CMOS CPU Chip Adaptable to Evolving Logic Design (1982) (19)
- Parametric yield optimization of CMOS analogue circuits by quadratic statistical circuit performance models (1991) (19)
- Compact Verilog-A model of phase-change RAM transient behaviors for multi-level applications (2011) (18)
- Simulation-based maximum power estimation (1996) (17)
- A self-regulating VCO with supply sensitivity of <0.15%-delay/1%-supply (2002) (17)
- Determining accuracy bounds for simulation-based switching activity estimation (1995) (17)
- Efficient transient electrothermal simulation of CMOS VLSI circuits under electrical overstress (1998) (16)
- Compensation modeling for QoS support on a wireless network (2000) (15)
- An efficient method for parametric yield optimization of MOS integrated circuits (1989) (15)
- Low-swing clock domino logic incorporating dual supply and dual threshold voltages (2002) (15)
- A new circuit optimization technique for high performance CMOS circuits (1991) (15)
- ESD design rule checker (2001) (15)
- Data-Dependent Statistical Memory Model for Passive Array of Memristive Devices (2010) (15)
- Memristor-based synapses and neurons for neuromorphic computing (2015) (15)
- Modeling, extraction and simulation of CMOS I/O circuits under ESD stress (1998) (15)
- Implication graph based domino logic synthesis (1999) (14)
- Fast temperature calculation for transient electrothermal simulation by mixed frequency/time domain thermal model reduction (2000) (14)
- Fast Computation of Temperature Profiles of VLSI ICs with High Spatial Resolution (2008) (14)
- A chip-level electrothermal simulator for temperature profile estimation of CMOS VLSI chips (1996) (14)
- Simulation of MOS circuit performance degradation with emphasis on VLSI design-for-reliability (1989) (14)
- Fast timing simulation for submicron hot-carrier degradation (1995) (14)
- Electrothermal simulation of electrical overstress in advanced nMOS ESD I/O protection devices (1993) (14)
- An integrated approach to realistic worst-case design optimization of MOS analog circuits (1992) (14)
- ESD protection for BiCMOS circuits (2000) (13)
- Modeling and simulation of the OETC optical bus (1995) (13)
- Domino logic synthesis minimizing crosstalk (2000) (13)
- 0.18um CMOS integrated chipset for 5.8GHz DSRC systems with +10dBm output power (2008) (13)
- Filter Design Using a New Field-Programmable Analog Array (FPAA) (1997) (13)
- A new global router using zero-one integer linear programming techniques for sea-of-gates and custom logic arrays (1992) (13)
- iCET: a complete chip-level thermal reliability diagnosis tool for CMOS VLSI chips (1996) (13)
- VeriCDF: a new verification methodology for charged device failures (2002) (13)
- OPTICAL 2R REMODULATOR USING FEEDFORWARD CONTROL OF SEMICONDUCTOR OPTICAL AMPLIFIER GAIN (1999) (13)
- An Efficient Transistor Folding Algorithm For Row-based Cmos Layout Design (1997) (13)
- Effective algorithms for cache-level compression (2001) (13)
- A compact Verilog-A model for Multi-Level-Cell Phase-change RAMs (2009) (13)
- A new triple-layer OTC channel router (1994) (13)
- How to Build a Memristive Integrate-and-Fire Model for Spiking Neuronal Signal Generation (2021) (12)
- Layout extraction and verification methodology CMOS I/O circuits (1998) (12)
- Full chip ESD design rule checking (2001) (12)
- Efficient approximation of the time domain response of lossy coupled transmission line trees (1995) (12)
- The iPOINT testbed for optoelectronic ATM networking (1993) (12)
- Low-power 2.4GHz CMOS frequency synthesizer with differentially controlled MOS varactors (2006) (12)
- Statistical estimation of average power dissipation using nonparametric techniques (1998) (12)
- Design of a 6 bit 1.25 GS/s DAC for WPAN (2008) (12)
- Design of ESD power protection with diode structures for mixed-power supply systems (2004) (11)
- MOMCO: method of moment components for passive model order reduction of RLCG interconnects (2001) (11)
- New simulation methods for MOS VLSI timing and reliability (1991) (11)
- Layout extraction and verification methodology for CMOS I/O circuits (1998) (11)
- Fast Evaluation Method for Transient Hot Spots in VLSI ICs in Packages (2008) (11)
- Modular Structure of Compact Model for Memristive Devices (2014) (11)
- Modular charge recycling pass transistor logic (MCRPL) (2000) (11)
- Fast- Frequency Offset Cancellation Loop Using Low-IF Receiver and Fractional-N PLL (2007) (11)
- Crosstalk noise minimization in domino logic design (2001) (11)
- EXODUS: inter-module bus-encoding scheme for system-on-a-chip (2000) (10)
- 3.48mW 2.4GHz range Frequency Synthesizer Architecture with Two-Point Channel Control for Fast Settling Performance (2005) (10)
- Analysis of a three-layered piezoelectric ceramic transformer filter (1995) (10)
- Noise-aware power optimization for on-chip interconnect (2000) (10)
- Interconnect simulation in a fast timing simulator ILLIADS-I (1999) (10)
- CMOS Pass-gate No-race Charge-recycling Logic (CPNCL) (1999) (10)
- Experimental validation of the power blurring method (2010) (10)
- Feasible region approximation using convex polytopes (1993) (10)
- Memristors-based Ternary Content Addressable Memory (mTCAM) (2014) (10)
- iTEM: a chip-level electromigration reliability diagnosis tool using electrothermal timing simulation (1996) (10)
- Memristor-based neural circuits (2013) (9)
- ILLIADS: a new fast MOS timing simulator using direct equation-solving approach (1991) (9)
- Energy-Efficient Memristive Analog and Digital Electronics (2012) (9)
- Circuit-Level Electrothermal Simulation (1995) (9)
- Improved domino structures effective for high performance design (1999) (9)
- Scanning the Special Issue on On-Chip Thermal Engineering (2006) (9)
- iRULE: fast hot-carrier reliability diagnosis using macro-models (1994) (9)
- Thermal failure simulation for electrical overstress in semiconductor devices (1993) (9)
- A timing-driven data path layout synthesis with integer programming (1995) (8)
- Hierarchical electromigration reliability diagnosis for VLSI interconnects (1996) (8)
- A High Speed Low-Power Accumulator for Direct Digital Frequency Synthesizer (2006) (8)
- Neuronal spike event generation by memristors (2012) (8)
- NMOS energy recovery logic (1999) (8)
- Chip-level thermal simulator to predict VLSI chip temperature (1995) (8)
- High performance CMOS macromodule layout synthesis (1994) (8)
- Circuit-level simulation and layout optimization for deep submicron EOS/ESD output protection device (1997) (8)
- Performance-Constrained Worst-Case Variability Minimization of VLSI Circuits (1993) (8)
- Genetic Algorithm Based Design Optimization Of CMOS VLSI Circuits (1994) (7)
- Noise-aware interconnect power optimization in domino logic synthesis (2003) (7)
- Noise constrained power optimization for dual V/sub T/ domino logic (2001) (7)
- Efficient algorithms for polygon to trapezoid decomposition and trapezoid corner stitching (2000) (7)
- Substrate thermal model reduction for efficient transient electrothermal simulation (2000) (7)
- Design of a neural stimulator system with closed-loop charge cancellation (2012) (7)
- High-level hot carrier reliability-driven synthesis using macro-models (1995) (7)
- On-chip thermal engineering for peta-scale integration (2002) (7)
- A 4-Gb/s/pin current mode 4-level simultaneous bidirectional I/O with current mismatch calibration (2006) (7)
- Substrate modeling and lumped substrate resistance extraction for CMOS ESD/latchup circuit simulation (1999) (7)
- Low-Variance Memristor-Based Multi-Level Ternary Combinational Logic (2022) (7)
- Differential pass-transistor clocked flipflop (2001) (7)
- System-Theoretic Methods for Designing Bio-Inspired Mem-Computing Memristor Cellular Nonlinear Networks (2021) (7)
- Energy-efficient skewed static logic with dual Vt: design and synthesis (2003) (7)
- Memristive computing- multiplication and correlation (2012) (7)
- Simulation of hot-carrier induced MOS circuit degradation for VLSI reliability analysis (1994) (6)
- SIMPLE CMOS TRANSITION ACCELERATOR CIRCUIT (1991) (6)
- Interconnect thermal modeling for determining design limits on current density (1999) (6)
- Scanning the issue interconnections - addressing the next challenge of IC technology (part II: design, characterization, and modeling) (2001) (6)
- Proceedings of the 11th Great Lakes symposium on VLSI (2000) (6)
- A low-power 1.85 GHz 32-bit carry lookahead adder using Dual Path All-N-Logic (2004) (6)
- New architectures for M4R shape coding (1998) (6)
- A low-power 2.1 GHz 32-bit carry lookahead adder using Dual Path All-N-Logic (2002) (5)
- An accurate intrinsic capacitance modeling for deep submicrometer MOSFET's (1995) (5)
- 1-GS/s, 12-bit SiGe BiCMOS D/A converter for high-speed DDFs (2003) (5)
- Parallel dynamic logic (PDL) with speed-enhanced skewed static (SSS) logic (2000) (5)
- Optimizing component specifications in optical interconnects using mixed-level simulation (1994) (5)
- Technology independent arbitrary device extractor (2000) (5)
- Model-order reduction of weakly nonlinear MEMS devices with Taylor series expansion and Arnoldi process (2000) (5)
- Analytical thermal placement for VLSI lifetime improvement and minimum performance variation (2007) (5)
- Transistor sizing for reliable domino logic design in dual threshold voltage technologies (2001) (5)
- Statistical estimation of short-circuit power in VLSI circuits (1996) (5)
- 21.3 A 2GHz 130mW direct-digital frequency synthesizer with a nonlinear DAC in 55nm CMOS (2014) (5)
- Domino logic synthesis based on implication graph (2002) (5)
- Gate leakage tolerant circuits in deep sub-100 nm CMOS technologies (2004) (5)
- Ultra Fast Calculation of Temperature Profiles of VLSI ICs in Thermal Packages Considering Parameter Variations (2007) (5)
- High-speed CMOS circuits with parallel dynamic logic and speed-enhanced skewed static logic (2002) (5)
- A 3-D Reconfigurable RRAM Crossbar Inference Engine (2021) (4)
- Design-for-ESD-reliability for high-frequency I/O interface circuits in deep-submicron CMOS technology (2001) (4)
- A mixed frequency-time approach for quasi-periodic steady-state simulation of multi-level modeled circuits (1999) (4)
- Fast settling frequency synthesizer with two‐point channel control paths (2012) (4)
- A study of hot-carrier-induced mismatch drift: a reliability issue for VLSI circuits (1998) (4)
- Low cost and high efficiency BIST scheme with 2-level LFSR and ATPT (2001) (4)
- New current-mode sense amplifiers for high density DRAM and PIM architectures (2001) (4)
- Complementary structure of memristive devices based passive memory arrays (2011) (4)
- Improvement on chip-level electrothermal simulator-ILLIADS-T (1996) (4)
- A Convex Programming Approach to Transistor Sizing (1993) (4)
- New high performance sub-1 V circuit technique with reduced standby current and robust data holding (2000) (4)
- Simulation of electrical overstress thermal failures in integrated circuits (1994) (4)
- Macrocell placement with temperature profile optimization (1999) (4)
- Timing constraints for domino logic gates with timing-dependent keepers (2003) (4)
- Logic transformation for low power synthesis (1999) (4)
- Circuit-level electrothermal simulation techniques for designing output protection devices (1994) (3)
- Accuracy bounds in switching activity estimation (1995) (3)
- Understanding and addressing the noise induced by electrostatic discharge in multiple power supply systems (2001) (3)
- A custom cell generation system for double-metal CMOS technology (1989) (3)
- Simulation of p-n junction properties of nanowires and nanowire arrays (2007) (3)
- Development of MEMS Vertical Planar Coil Inductors Through Plastic Deformation Magnetic Assembly ( PDMA ) (2002) (3)
- A Parametric Macro-model Approach For Hot-carrier Resistant MOS Vlsi Design (1992) (3)
- Nanoscience and Nanotechnology: Status, Potential and Roadmap (2006) (3)
- Nonparametric estimation of average power dissipation in CMOS VLSI circuits (1996) (3)
- Fast thermal analysis for CMOS VLSIC reliability (1996) (3)
- High-performance, low-power skewed static logic in very deep-submicron (VDSM) technology (2000) (3)
- Multiple trigonometric approximation of sine-amplitude with small ROM size for direct digital frequency synthesizers (2003) (3)
- Unified modeling for memristive devices based on charge-flux constitutive relationships (2013) (3)
- FPGA Synthesis of Ternary Memristor-CMOS Decoders (2021) (3)
- An analytic method to calculate emitter follower delay using trial functions in coupled node equations (1995) (3)
- Energy-efficient skewed static logic design with dual Vt (2001) (3)
- A sequential procedure for average power analysis of sequential circuits (1997) (3)
- The engineering research center for compound semiconductor microelectronics (1993) (2)
- A low-power reduced swing single clock flip-flop (2001) (2)
- Temperature-driven power and timing analysis for CMOS ULSI circuits (1999) (2)
- 2.4GHz ZigBee radio architecture with fast frequency offset cancellation loop (2006) (2)
- Functional verification of ECL circuits including voltage regulators (1993) (2)
- A Design of CMOS Polycells for LSI Circuits (1999) (2)
- Life-range-delimitation optical transceiver for fast routing and multicasting in WDM optical networks (1994) (2)
- Quality of service support for heterogeneous traffic across hybrid wired and wireless networks (2001) (2)
- Modeling and simulation of metal-semiconductor-metal photodetector using VHDL-AMS (2004) (2)
- Memristor-Based Resistive Computing (2014) (2)
- Efficient modeling and simulation of coupled transmission lines (1995) (2)
- Development of a MEMS Vertical Planar Coil Inductor (2002) (2)
- Interconnections-addressing the next challenge of IC technology (part I: integration and packaging trends) (2001) (2)
- Logic transformation for low-power synthesis (2002) (2)
- Dual threshold voltage domino logic synthesis for high performance with noise and power constraint (2002) (2)
- Memristor macromodel and its application to neuronal spike generation (2013) (2)
- No-race charge-recycling differential logic (NCDL) (1999) (2)
- ABR architecture and simulation for an input-buffered and per-VC queued ATM switch (1998) (2)
- An efficient method for circuit sensitivity calculation using piecewise linear waveform models (1988) (2)
- Computer-aided design of mixed-technology VLSI systems (2000) (2)
- An algorithm for functional verification of digital ECL circuits (1995) (2)
- Electromechanical and microwave S-parameter properties of a wide tuning range MEMS tunable capacitor (2001) (2)
- Optimal timing for skew-tolerant high-speed domino logic (2002) (2)
- Issues in the modeling of fiber optic systems (1995) (1)
- Optimal design of leak-proof SRAM cell using MCDM method (2003) (1)
- Oxide-Tunneling Leakage Suppressed SRAM for Sub-65-nm Very Large Scale Integrated Circuits (2011) (1)
- From 100 milliwatts/MIPS to 10 microwatts/MIPS [low-power VLSI] (1994) (1)
- Noise-aware design for ESD reliability in mixed-signal integrated circuits (2001) (1)
- ServerNet and ATM interconnects: Comparison for compressed video transmission (1999) (1)
- Low Power Flip-Flop and Clock Network Design Methodologies in High-Performance System-on-a-Chip (2002) (1)
- Memristors, memristive devices and systems in nano era (2009) (1)
- Modeling of Degradation Mechanisms (1993) (1)
- Current mode multi-level simultaneous bidirectional I/O scheme for chip-to-chip communications (2005) (1)
- Incremental node extraction algorithms for incremental layout system (1995) (1)
- Three-Dimensional ElectroThermal Modeling of Thin Film Micro-Refrigerators for Site-Specific Cooling of VLSI ICs (2006) (1)
- VLSI Design for Reliability - Hot Electron (1992) (1)
- The State of Service Protocols (2000) (1)
- A low glitch SiGe BiCMOS current switch for high performance D/A converters (2001) (1)
- Performance comparison of video transport over ATM and ServerNet interconnects (1997) (1)
- Elements of CMOS VLSI System Design (1985) (1)
- Coupling-aware minimum delay optimization for domino logic circuits (2001) (1)
- AUTOMATIC CIRCUIT SYNTHESIS FOR MULTILEVEL METAL MOS TECHNOLOGY (1989) (1)
- Average power analysis of sequential circuits using an autoregressive model (1998) (1)
- Design limitations in deep sub-0.1μm CMOS SRAM (2002) (1)
- Singularities of Nonlinear Circuit Theory and Applications: Achievements of Professor Leon Ong Chua (2018) (1)
- Maximizing power harvest in a distributed photovoltaic system (2012) (1)
- A low-voltage high-speed BiCMOS current switch with enhanced-spectral performance (2002) (1)
- A New Tunneling Barrier Width Model of the Switching Mechanism in Hafnium Oxide-Based Resistive Random Access Memory (2010) (1)
- High performance dynamic logic incorporating gate voltage controlled keeper structure for wide fan-in gates (2002) (1)
- Performance driven cell generator for dynamic CMOS circuits (1989) (1)
- 2-level LFSR scheme with asynchronous test pattern transfer for low cost and high efficiency build-in-self-test (2001) (1)
- Estimating node voltages in bipolar circuits using linear programming (1995) (1)
- Data Link Level Support for Handoff in ATM Network (1997) (1)
- Improving the semiconductor optical amplifier switching speed using a pre-impulse-step injected current (1)
- Programmable High Speed Multi-Level Simultaneous Bidirectional I/O (2007) (1)
- Oxide Degradation Mechanisms in MOS Transistors (1993) (1)
- Interconnection Delay in Very (1991) (1)
- Macromodeling of Hot-Carrier Induced Degradation in Mos Circuits (1993) (1)
- Noise-constrained design of reliable power networks for mixed-power supply systems (2001) (1)
- Circuit-Level Simulation for Failure Analysis of Advanced CMOS ESD Protection Structures (1997) (1)
- Electrical Overstress in Integrated Circuits (1995) (1)
- Transistor-Level Simulation for Circuit Reliability (1993) (0)
- New word-line driving scheme for suppressing oxide-tunneling leakage in sub-65-nm SRAMs (2009) (0)
- The Dave I Know: In Memory of Late Professor Chung Laung "David" Liu [Society News] (2021) (0)
- Forum: From 100 Milliwatts/MIPS to 10 Microwatts/MIPS (1994) (0)
- Trapezoid-to-simple polygon recomposition for resistance extraction (2001) (0)
- An Optimal Design of LeakProof SRAM Cell Using MCDM Method (0)
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- EOS Thermal Failure Simulation for Integrated Circuits (1995) (0)
- IETSIM : An Electrothermal Circuit Simulator (1995) (0)
- Transistor Sizing Algorithms: Existing Approaches (1993) (0)
- Fast temperature calculation for transient electrothermal simulation by mixed frequency/time domainirhermal model reduction (2000) (0)
- Low-power skewed static logic (S/sup 2/L) with topology-dependent dual Vt (2000) (0)
- Nanosession: Neuromorphic Concepts (2013) (0)
- Keynote Speech Abstracts; 1. Nanoscience and Nanotechnology: Status, Potential and Roadmap (2006) (0)
- Prototype Rule-Based Reliability Analysis for VLSI Circuit Design (1994) (0)
- Design and Power Analysis of Memory System using Conventional 6T, Sleepy Stack 8T and Single Ended 6T SRAM cell (2020) (0)
- Timing-driven CMOS Layout Synthesis (1993) (0)
- Measuring EOS Robustness in Integrated Circuits (1995) (0)
- An efficient calibration technique for systematic current-mismatch of D/A converters (2003) (0)
- A STUDY OF WORST-CASE INTEGRATED CIRCUIT OPTIMIZATION USING IEDISON3.0 BY JOHN (2020) (0)
- Fringing field effects in semiconductor nanowire double heterostructures (2009) (0)
- VLSI Design for Reliability-Hot Carrier Effects (1993) (0)
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- NMOS ESD Protection Devices and Process Related Issues (1995) (0)
- Global Routing Using Zero-one Integer Linear Programming (1993) (0)
- Understanding linearity range of 1GHz-VCO with 1.8V LDO (2020) (0)
- Memristive trans-impedance amplifier (mTIA) and its application to DNA sequencing (2014) (0)
- Summary and Future Research (1995) (0)
- Power efficient high-speed DAC for wideband communication applications (2012) (0)
- Modeling of Circuit Performances (2001) (0)
- Hierarchical partitioning of high-level VHDL structures (1994) (0)
- Coupling-aware minimum delay optimisation for domino logic circuits (2001) (0)
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- A new domino failure mechanism in deep sub-100-nm technologies and its solution (2004) (0)
- Physical design for giga scale CMOS VLSI (1994) (0)
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- Modeling of Damaged Mosfets (1993) (0)
- Signal Encoding Schemes for Low-Power Interface Design (2000) (0)
- Introduction to IEEE CASM Special Issue [From the Guest Editors] (2016) (0)
- Modeling, simulation and layout synthesis for giga scale CMOS VLSI (1994) (0)
- A Design of 1GSamples/s 6-Bit Flash A/D Converter with Current-mode Amplifiers & Comparators (2003) (0)
- Fast Timing Simulation for Circuit Reliability (1993) (0)
- Data link level support for handoff in wireless ATM network (1997) (0)
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- Proceedings of the 11th ACM Great Lakes Symposium on VLSI 2001, West Lafayette, Indiana, USA, 2001 (2001) (0)
- When bad things happen to good chips (panel session) (2000) (0)
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