Timothy M. Pinkston | Academic Influence

Timothy M. Pinkston's AcademicInfluence.com Rankings

Timothy M. Pinkston

Engineering

#7861

World Rank

#9302

Historical Rank

#1393

USA Rank

Electrical Engineering

#2631

World Rank

#2765

Historical Rank

#347

USA Rank

engineering Degrees

Timothy M. Pinkston

Computer Science

#10473

World Rank

#11001

Historical Rank

#1826

USA Rank

Computer Architecture

#78

World Rank

#80

Historical Rank

#32

USA Rank

Computer Engineering

#173

World Rank

#175

Historical Rank

#18

USA Rank

computer-science Degrees

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Engineering
Computer Science

Timothy M. Pinkston's Degrees

PhD Electrical Engineering University of Southern California
Masters Electrical Engineering University of Southern California
Bachelors Electrical Engineering University of Southern California

Why Is Timothy M. Pinkston Influential?

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According to Wikipedia, Timothy M. Pinkston is an American computer engineer, researcher, educator and administrator whose work is focused in the area of computer architecture. He holds the George Pfleger Chair in Electrical and Computer Engineering and is a Professor of Electrical and Computer Engineering at University of Southern California . He also serves in an administrative role as Vice Dean for Faculty Affairs at the USC Viterbi School of Engineering.

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Timothy M. Pinkston's Published Works

Number of citations in a given year to any of this author's works

Total number of citations to an author for the works they published in a given year. This highlights publication of the most important work(s) by the author

Published Works

An efficient, fully adaptive deadlock recovery scheme: DISHA (1995) (178)
NoRD: Node-Router Decoupling for Effective Power-gating of On-Chip Routers (2012) (153)
A Lightweight Fault-Tolerant Mechanism for Network-on-Chip (2007) (140)
A Proactive Wearout Recovery Approach for Exploiting Microarchitectural Redundancy to Extend Cache SRAM Lifetime (2008) (111)
A methodology for designing efficient on-chip interconnects on well-behaved communication patterns (2003) (111)
Power punch: Towards non-blocking power-gating of NoC routers (2015) (96)
A General Theory for Deadlock-Free Adaptive Routing Using a Mixed Set of Resources (2001) (95)
On Deadlocks In Interconnection Networks (1997) (88)
A Progressive Approach to Handling Message-Dependent Deadlock in Parallel Computer Systems (2003) (85)
DISHA: a deadlock recovery scheme for fully adaptive routing (1995) (80)
Deadlock-Free Dynamic Reconfiguration Schemes for Increased Network Dependability (2003) (79)
Generalized theory for deadlock-free adaptive wormhole routing and its application to Disha Concurrent (1996) (72)
Characterizing the Cell EIB On-Chip Network (2007) (68)
Software-based deadlock recovery technique for true fully adaptive routing in wormhole networks (1997) (66)
An Efficient and Deadlock-Free Network Reconfiguration Protocol (2008) (61)
MP3: Minimizing performance penalty for power-gating of Clos network-on-chip (2014) (58)
Flexible and Efficient Routing Based on Progressive Deadlock Recovery (1999) (47)
A theory for deadlock-free dynamic network reconfiguration. Part I (2005) (45)
A design methodology for efficient application-specific on-chip interconnects (2006) (43)
Characterization of Deadlocks in k-ary n-Cube Networks (1999) (42)
TAPP: Temperature-aware application mapping for NoC-based many-core processors (2015) (41)
Worm-Bubble Flow Control (2013) (40)
On Characterizing Performance of the Cell Broadband Engine Element Interconnect Bus (2007) (39)
Simple Deadlock-Free Dynamic Network Reconfiguration (2004) (39)
Critical Bubble Scheme: An Efficient Implementation of Globally Aware Network Flow Control (2011) (38)
Characterization of deadlocks in interconnection networks (1997) (37)
A Formal Model of Message Blocking and Deadlock Resolution in Interconnection Networks (2000) (37)
Trends toward on-chip networked microsystems (2005) (35)
A methodology for developing deadlock-free dynamic network reconfiguration processes. Part II (2005) (31)
Evaluation of a subnet management mechanism for InfiniBand networks (2003) (30)
Communication-Aware Globally-Coordinated On-Chip Networks (2012) (29)
The double scheme: deadlock-free dynamic reconfiguration of cut-through networks (2000) (27)
High Performance Computing - HiPC 2003 (2003) (26)
Evaluation of queue designs for true fully adaptive routers (2002) (25)
The SPEED cache coherence protocol for an optical multi-access interconnect architecture (1995) (24)
Characterization of deadlocks in irregular networks (1999) (24)
Bubble coloring: avoiding routing- and protocol-induced deadlocks with minimal virtual channel requirement (2013) (22)
SPEED DMON: Cache Coherence on an Optical Multichannel Interconnect Architecture (1997) (21)
Design of an optical reconfigurable shared-bus-hypercube interconnect. (1994) (21)
On the Infiniband subnet discovery process (2003) (21)
A new mechanism for congestion and deadlock resolution (2002) (18)
Deadlock-free dynamic reconfiguration over InfiniBand™ NETWORKS (2004) (17)
A methodology for developing dynamic network reconfiguration processes (2003) (16)
Smart-pixel-based network interface chip. (1997) (15)
Distributed resolution of network congestion and potential deadlock using reservation-based scheduling (2005) (14)
Design considerations for optical interconnects in parallel computers (1994) (14)
WARRP Core: Optoelectronic Implementation of Network-Router Deadlock-Handling Mechanisms. (1998) (13)
A New Token-Based Channel Access Protocol for Wavelength Division Multiplexed Multiprocessor Interconnects (2000) (13)
Evaluation of Crossbar Architectures for Deadlock Recovery Routers (2001) (12)
The Performance of Routing Algorithms under Bursty Traffic Loads (2003) (12)
Simulation of NoC power-gating: Requirements, optimizations, and the Agate simulator (2016) (11)
Balancing On-Chip Network Latency in Multi-application Mapping for Chip-Multiprocessors (2014) (10)
Crossbar analysis for optimal deadlock recovery router architecture (1997) (10)
An Analytical Performance Model for Partitioning Off-Chip Memory Bandwidth (2013) (10)
Parallel Processor Memory Reference Analysis: Examining Locality and Clustering Potential (1991) (10)
A clustering approach in characterizing interconnection networks (1998) (8)
WARRP II: an optoelectronic fully adaptive network router chip (1998) (8)
Smart Butterfly: Reducing static power dissipation of network-on-chip with core-state-awareness (2014) (8)
On Message.Dependent Deadlocks in Multiprocessor/Multicomputer Systems (2000) (8)
InfiniBand: The “De Facto” Future Standard for System and Local Area Networks or Just a Scalable Replacement for PCI Buses? (2003) (7)
An asynchronous optical token smart-pixel design based on hybrid CMOS-SEED integration (1996) (7)
Report for the NSF Workshop on Cross ‐ layer Power Optimization and Management (2012) (7)
Design issues for core-based optoelectronic chips: a case study of the WARRP network router (1999) (7)
Modeling Free-Space Optical k-ary n-Cube Wormhole Networks (1998) (6)
Applying Optical Interconnects to the 3-D Computer: A Performance Evaluation (1986) (6)
Thread criticality support in on-chip networks (2010) (5)
An optical interconnect model for k-ary n-cube wormhole networks (1996) (5)
RAIR: Interference Reduction in Regionalized Networks-on-Chip (2013) (5)
A hybrid cache coherence protocol for a decoupled multi-channel optical network: SPEED DMON (1996) (4)
PAIS: Parallelism-aware interconnect scheduling in multicores (2014) (4)
A Method for Applying Double Scheme Dynamic Reconfiguration over InfiniBandTM (2003) (4)
Efficient handling of message-dependent deadlock (2001) (4)
Deadlock Characterization and Resolution in Interconnection Networks (2004) (4)
Providing Balanced Mapping for Multiple Applications in Many-Core Chip Multiprocessors (2016) (4)
Cubic Ring Networks: A Polymorphic Topology for Network-on-Chip (2010) (4)
Lifetime reliability studies for microprocessor chip architecture (2008) (3)
Modeling Message Blocking and Deadlock in Interconnection Networks (1997) (3)
Architecture and Optoelectronic Implementation of the WARRP Router (2007) (3)
Smart-Pixel Implementation of Network Router Deadlock Handling Mechanisms (1997) (2)
Performance analysis of unstructured peer-to-peer schemes in integrated wired and wireless network environments (2005) (2)
Buses and Crossbars (2011) (2)
Parallel Processor Memory Reference Analysis and its Application to Interconnect Architecture (1990) (2)
Bulk Synchronous Parallelism (BSP) (2011) (2)
PAIS (2014) (2)
A Token-based Channel Access Protocol for Wavelength Division Multiplexed Optically Interconnected Multiprocessors (2000) (1)
A clustering approach for identifying and quantifying irregularities in interconnection networks (2003) (1)
Evaluation of design issues for optoelectronic cores: a case study of the WARRP II router (1999) (1)
Guest Editorial: Special Section on On-Chip Networks (2005) (1)
Implementation of Deadlock Detection in a Simulated Network Environment (1997) (1)
A High-Performance Optoelectronic Interconnect Router : Using Increased Bandwidth to Enable Latency Reduction (1997) (0)
Peer-to-peer caching schemes for integrated wired and wireless network environments (2005) (0)
Message from the Program Chair (2022) (0)
Proceedings, International Conference on Parallel Processing Workshops, 3-7 September 2001, Valencia, Spain (2001) (0)
Engineering an Educational Transformation Based on Analogies with Chemical Reaction and Flow Processes1 (2018) (0)
OMNI: An optoelectronic multichannel network interface based on hybrid CMOS-SEED technology (1996) (0)
チップ内ネットワーク向け軽量な耐故障機構(ネットワークとシミュレーション技術,コンピュータシステムのインタコネクト技術及び一般) (2007) (0)
A System Demonstration of Progressive Deadlock Recovery Routing based on Optoelectronic/VLSI Chips (1997) (0)
2 . MASSAGE BLOCKING AND DEADLOCKS IN IRREGULAR NETWORKS 2 (2001) (0)
Topic Introduction (2003) (0)
IPDPS 2007 Organization (2007) (0)
IPDPS 2007 Organization (2007) (0)
Bsp (2020) (0)
Computer engineering using innovative instructional technologies at the University of Southern California (1998) (0)
A HYBRID CACHE COHERENCE PROTOCOL OPTICAL NETWORK: SPEED DMON * FOR A DECOUPLED MULTI-CHANNEL (1996) (0)
[13] J. Duato. A Necessary and Sufficient Condition for (1992) (0)
Throughput enhancement of an electronic multiprocessor by the coupling of an optical coprocessor (1990) (0)
Optical Co-processor Studies (1992) (0)
Proceedings of the 2006 International Conference on Parallel Processing Workshops, 14-18 August 2006, Columbus, Ohio (2006) (0)

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