Tom Conte
#44,753
Most Influential Person Now
American computer scientist
Tom Conte's AcademicInfluence.com Rankings
Tom Contecomputer-science Degrees
Computer Science
#2255
World Rank
#2349
Historical Rank
#1014
USA Rank
Computer Architecture
#24
World Rank
#24
Historical Rank
#19
USA Rank
Database
#8684
World Rank
#9108
Historical Rank
#1175
USA Rank
Download Badge
Computer Science
Why Is Tom Conte Influential?
(Suggest an Edit or Addition)According to Wikipedia, Thomas Martin Conte is the Associate Dean for Research and Professor of Computer Science at Georgia Institute of Technology College of Computing; and, since 2011, also Professor of Electrical and Computer Engineering at Georgia Institute of Technology College of Engineering. He is a fellow of Institute of Electrical and Electronics Engineers . He served as the president of the IEEE Computer Society in 2015.
Tom Conte's Published Works
Number of citations in a given year to any of this author's works
Total number of citations to an author for the works they published in a given year. This highlights publication of the most important work(s) by the author
Published Works
- A Benchmark Characterization of the EEMBC Benchmark Suite (2009) (214)
- Reducing state loss for effective trace sampling of superscalar processors (1996) (193)
- Unified assign and schedule: a new approach to scheduling for clustered register file microarchitectures (1998) (171)
- Optimization of instruction fetch mechanisms for high issue rates (1995) (170)
- Adaptive mode control: A static-power-efficient cache design (2003) (159)
- Configurable string matching hardware for speeding up intrusion detection (2005) (132)
- PARALLEL AND DISTRIBUTED SYSTEMS (2010) (129)
- Performance Analysis and Its Impact on Design (1998) (114)
- Treegion scheduling for wide issue processors (1998) (89)
- Challenges to Combining General-Purpose and Multimedia Processors (1997) (88)
- Comparing Software And Hardware Schemes For Reducing The Cost Of Branches (1989) (87)
- Compiler-driven cached code compression schemes for embedded ILP processors (1999) (83)
- The Effect of Code Expanding Optimizations on Instruction Cache Design (1993) (80)
- Instruction fetch mechanisms for VLIW architectures with compressed encodings (1996) (77)
- Enhancing memory-level parallelism via recovery-free value prediction (2003) (73)
- Combining Trace Sampling with Single Pass Methods for Efficient Cache Simulation (1998) (66)
- Dynamic rescheduling: a technique for object code compatibility in VLIW architectures (1995) (62)
- Value speculation scheduling for high performance processors (1998) (54)
- Benchmark characterization (1991) (53)
- Accurate and practical profile-driven compilation using the profile buffer (1996) (53)
- Adaptive mode control: a static-power-efficient cache design (2001) (48)
- Systematic computer architecture prototyping (1992) (48)
- Embedded Multicore Processors and Systems (2009) (48)
- Using branch handling hardware to support profile-driven optimization (1994) (47)
- Proceedings of the international symposium on Code generation and optimization: feedback-directed and runtime optimization (2003) (46)
- Benchmark characterization for experimental system evaluation (1990) (44)
- Detecting global stride locality in value streams (2003) (42)
- System-level power consumption modeling and tradeoff analysis techniques for superscalar processor design (2000) (38)
- Weld: A Multithreading Technique Towards Latency-Tolerant VLIW Processors (2001) (33)
- Energy efficient Phase Change Memory based main memory for future high performance systems (2011) (32)
- Treegion Scheduling for Highly Parallel Processors (1997) (31)
- Fast Simulation of Computer Architectures (1995) (30)
- Rebooting Computing: The Road Ahead (2017) (29)
- Architectures for the Post-Moore Era (2017) (28)
- Thinwire protocol for connecting personal computers to the Internet (1984) (28)
- A lightweight algorithm for dynamic if-conversion during dynamic optimization (2000) (25)
- Manager-client pairing: A framework for implementing coherence hierarchies (2011) (23)
- High-performance and low-cost dual-thread VLIW processor using Weld architecture paradigm (2005) (23)
- A fast interrupt handling scheme for VLIW processors (1998) (22)
- Code size efficiency in global scheduling for ILP processors (2002) (21)
- The Susceptibility of Programs to Context Switching (1994) (20)
- Compilers for Instruction-Level Parallelism (1997) (20)
- Challenges in processor modeling and validation [Guest Editors?? introduction] (1999) (18)
- Sustaining Moore’s Law with 3D Chips (2017) (18)
- Standards: Roadmapping Computer Technology Trends Enlightens Industry (2018) (18)
- Subword extensions for video processing on mobile systems (1998) (18)
- A technique to determine power-efficient, high-performance superscalar processors (1995) (17)
- Rebooting Computing and Low-Power Image Recognition Challenge (2015) (17)
- Contech: Efficiently Generating Dynamic Task Graphs for Arbitrary Parallel Programs (2015) (15)
- Software-Only Value Speculation Scheduling (1998) (14)
- Treegion Scheduling for Vliw Processors (1997) (14)
- Exploiting program redundancy to improve performance, cost and power consumption in embedded systems (2000) (14)
- MPS: Miss-Path Scheduling for Multiple-Issue Processors (1998) (13)
- The Superstrider Architecture: Integrating Logic and Memory Towards Non-Von Neumann Computing (2017) (13)
- Benchmark characterization (1991) (12)
- Path prediction for high issue-rate processors (1997) (12)
- Tradeoffs In Processor/memory Interfaces For Superscalar Processors (1992) (12)
- Instruction scheduling and fetch mechanisms for clustered vliw processors (1998) (12)
- Guest Editors' Introduction: Challenges in Processor Modeling and Validation (1999) (12)
- Parallel Pattern Detection for Architectural Improvements (2011) (12)
- Length adaptive processors: a solution for the energy/performance dilemma in embedded systems (2009) (11)
- Determining cost-effective multiple issue processor designs (1993) (11)
- A study of value speculative execution and misspeculation recovery in superscalar microprocessors (2000) (11)
- Guest Editors' Introduction: Opportunities and Challenges in Embedded Systems (2004) (11)
- Accelerating Multi-threaded Application Simulation through Barrier-Interval Time-Parallelism (2012) (10)
- Tree Traversal Scheduling: A Global Scheduling Technique for VLIW/EPIC Processors (2001) (10)
- Hardware-Based Profiling: An Effective Technique for Profile-Driven Optimization (1996) (10)
- Spectral prefetcher: An effective mechanism for L2 cache prefetching (2005) (10)
- Reverse State Reconstruction for Sampled Microarchitectural Simulation (2007) (10)
- A brief survey of benchmark usage in the architecture community (1991) (9)
- MetaStrider: Architectures for Scalable Memory-centric Reduction of Sparse Data Streams (2020) (9)
- The Impact of Diversity on Online Ensemble Learning in the Presence of Concept Drift (2010) (9)
- Tackling memory access latency through DRAM row management (2018) (9)
- Programming Strategies for Irregular Algorithms on the Emu Chick (2018) (9)
- Experimental Insights from the Rogues Gallery (2019) (9)
- Proceedings of the 30th annual ACM/IEEE international symposium on Microarchitecture (1997) (8)
- A persistent rescheduled-page cache for low overhead object code compatibility in VLIW architectures (1996) (8)
- Rebooting Computing: New Strategies for Technology Scaling (2015) (8)
- Future High Performance Computing Capabilities: Summary Report of the Advanced Scientific Computing Advisory Committee (ASCAC) Subcommittee (2019) (7)
- High-speed formal verification of heterogeneous coherence hierarchies (2013) (7)
- Choosing the Brain(s) of an Embedded System (2002) (7)
- Extending Moore’s Law via Computationally Error-Tolerant Computing (2018) (7)
- Computationally-redundant energy-efficient processing for y'all (CREEPY) (2016) (7)
- Distributed Line Graphs: A Universal Technique for Designing DHTs Based on Arbitrary Regular Graphs (2012) (7)
- Optimal chip-package codesign for high-performance DSP (2005) (6)
- Dynamically programmable cache (1998) (6)
- Superstrider associative array architecture: Approved for unlimited unclassified release: SAND2017-7089 C (2017) (6)
- NextPC computation for a banked instruction cache for a VLIW architecture with a compressed encoding (1996) (6)
- Basic Research Needs for Microelectronics: Report of the Office of Science Workshop on Basic Research Needs for Microelectronics, October 23 – 25, 2018 (2018) (6)
- Any-size instruction abbreviation technique for embedded DSPs (2002) (6)
- Code Size Efficiency in Global Scheduling for VLIW / EPIC Style Embedded Processors 1 (2002) (6)
- Architectural resource requirements of contemporary benchmarks: a wish list (1993) (5)
- Properties of Rescheduling Size Invariance for Dynamic Rescheduling-Based VLIW Cross-Generation Compatibility (2000) (5)
- Proceedings of the 2021 International Conference on Compilers, Architectures, and Synthesis for Embedded Systems (2003) (5)
- A Case for Exploiting Memory-Access Persistence (2001) (5)
- Hardware-Based Pro ling: An E ective Technique for Pro le-Driven Optimization (1996) (5)
- Rebooting Computers to Avoid Meltdown and Spectre (2018) (5)
- Combining cluster sampling with single pass methods for efficient sampling regimen design (2007) (5)
- Compiler-driven value speculation scheduling (2001) (5)
- Computer design strategy for MCM-D/flip-chip technology (1996) (5)
- Special Session: Exploring the Ultimate Limits of Adiabatic Circuits (2020) (4)
- Commercializing profile-driven optimization (1995) (4)
- Memory System Design for Ultra Low Power, Computationally Error Resilient Processor Microarchitectures (2018) (4)
- A Treegion-based Unified Approach to Speculation and Predication in Global Instruction Scheduling (2001) (4)
- Bipartitioning for hybrid FPGA-software simulation (1996) (4)
- Optimization of VLIW compatibility systems employing dynamic rescheduling (1997) (4)
- Tree Traversal Scheduling: A Global Instruction Scheduling Technique for VLIW/EPIC Processors (2001) (3)
- Dynamically Programmable Cache Evaluation and Virtualization (1999) (3)
- Insight, not (random) numbers (2005) (3)
- Single-Pass Memory System Evaluation for Multiprogramming Workloads (1990) (3)
- Intrepydd: performance, productivity, and portability for data science application kernels (2020) (3)
- Contech (2015) (3)
- Improving DRAM Bandwidth Utilization with MLP-Aware OS Paging (2016) (3)
- Adaptive Mode-Control : A Low-Leakage , Power-Efficient Cache Design (2000) (3)
- Energy efficiency limits of logic and memory (2016) (3)
- Modeling Value Speculation: An Optimal Edge Selection Problem (2003) (3)
- Advances in Benchmarking Techniques: New Standards and Quantitative Metrics (1995) (2)
- Scheduling for Low Power Dissipation in High Performance (1998) (2)
- Performance Modeling of Memory Latency Hiding Techniques (2002) (2)
- Systematic prototyping of superscalar computer architectures (1992) (2)
- A Simulation Study of Simultaneous Vector Prefetch Performance in Multiprocessor Memory Subsystems (Extended Abstract) (1989) (2)
- Dual-thread Weld : A Technique for Latency Tolerance in Horizontal Architectures (2003) (2)
- Commercializing Pro le-Driven Optimization (1995) (2)
- Treegion Instruction Scheduling in GCC (2006) (2)
- A Brief Survey of Non-Residue Based Computational Error Correction (2016) (2)
- Stack-Based Single-Pass Cache Simulation (1995) (1)
- Technology Solutions for the Enterprise (2015) (1)
- The Effects of Traditional Compiler Optimizations on Superscalar Architectural Design (1994) (1)
- Using performance bounds to guide code compilation and processor design (2003) (1)
- Using Performance Bounds to Guide Pre-scheduling Code Optimizations (2005) (1)
- Importance of profiling and compatibility (1996) (1)
- A Power Model for Register-Sharing Structures (2008) (1)
- Dynamically programmable cache evaluation and virtualization (abstract only) (1999) (1)
- Staff Listing (2012) (1)
- Contech: A Tool for Analyzing Parallel Programs (2013) (1)
- Combining Sampling with Single-Pass Techniques for Efficient Cache Simulation (1991) (1)
- Scalable Energy-Efficient Microarchitectures With Computational Error Tolerance Via Redundant Residue Number Systems (2022) (1)
- Wrangling Rogues: A Case Study on Managing Experimental Post-Moore Architectures (2019) (1)
- iction for High Issue-Rate Processors (1997) (1)
- Extrapolation Pitfalls When Evaluating Limited Endurance Memory (2012) (1)
- Emerging Technologies: Can Optimization Technology meet their Demands? (Dagstuhl Seminar 03071) (2021) (1)
- On power and energy trends of IEEE 802.11n PHY (2009) (1)
- Evolutionary Compilation to Long Instruction Superscalar Microarchitectures for Exploiting Parallelism At All Levels (1998) (1)
- Proceedings of the Twenty-First International Conference on Architectural Support for Programming Languages and Operating Systems (2016) (1)
- The Computer Society Must Change (2015) (0)
- Iterative Modulo Scheduling (2018) (0)
- Preliminary filling a cache in thread migration (2010) (0)
- SortCache: Intelligent Cache Management for Accelerating Sparse Data Workloads (2021) (0)
- 2018 IEEE 42nd Annual Computer Software and Applications Conference, COMPSAC 2018, Tokyo, Japan, 23-27 July 2018, Volume 2 (2018) (0)
- Editor's Introduction (2004) (0)
- Combining General-purpose And Multimedia In Challenges And Opportunities Task Force Introduction (1997) (0)
- knowledge and data engineering A publication of the IEEE Computer Society (2005) (0)
- CONTE, HIRSCH, HWU: SINGLE PASS METHODS FOR EFFICIENT CACHE SIMULATION 1 Combining Trace Sampling with Single Pass Methods for E cient Cache Simulation (0)
- Cache Designs for a Class of Statically Scheduled Instruction Level Parallel Architectures (2007) (0)
- Keynote: Insight, Not (Random) Numbers: An Embedded Perspective (2007) (0)
- 41st IEEE Annual Computer Software and Applications Conference. 2 (2017) (0)
- DATA COMPRESSION AND NETWORK PROCESSING FOR POLYMORPHOUS COMPUTING ARCHITECTURE (PCA) (2005) (0)
- Session details: Keynote Address II (2016) (0)
- “Smarter” NICs for faster molecular dynamics: a case study (2022) (0)
- SPECIAL SECTION on Rule Representation Guest Editors' Introduction: Rule Representation, Interchange, and Reasoning in Distributed, (2010) (0)
- SortCache (2021) (0)
- Energy-aware opcode design (2008) (0)
- Parallel Processing, Superscalar and Vliw Processors (1999) (0)
- Editors' Introduction (2004) (0)
- Routing via multi-core networks using real world data or modeled data (2009) (0)
- High Performance Embedded Architectures and Compilers, First International Conference, HiPEAC 2005, Barcelona, Spain, November 17-18, 2005, Proceedings (2005) (0)
- Nanotechnology ‐ Inspired Grand Challenge Above and Beyond Exascale Computing : Sensible Machines (0)
- Keynote Talk #2 (2005) (0)
- Current Trends Challenges in Processor Modeling and Validation in This Issue (0)
- Fast Simulation of Computer Architectures: Introduction (1994) (0)
- Application Performance of Physical System Simulations (2019) (0)
- Proposed EPIC Instruction Semantics for Value Speculation Scheduling (1998) (0)
- Enabling Multi-threading in Heterogeneous Quantum-Classical Programming Models (2023) (0)
- Combining General-Purpose and Multimedia in One Package: Challenges and Opportunities (1997) (0)
- Proceedings of the 2005 International Conference on Compilers, Architecture, and Synthesis for Embedded Systems, CASES 2005, San Francisco, California, USA, September 24-27, 2005 (2005) (0)
- Insight, not (random) numbers: an embedded perspective (2007) (0)
- MetaStrider (2019) (0)
- 1 Performance Modeling of Memory Latency Hiding Techniques (2002) (0)
- Proceedings of the International Conference on Compilers, Architectures and Synthesis for Embedded Systems, CASES 2003, San Jose, California, USA, October 30 - November 1, 2003 (2003) (0)
- A configurable Classification Engine for Polymorphous Chip Architecture (2004) (0)
- Split Point Selection and Recovery for Value Speculation Scheduling (2007) (0)
- SPECIAL SECTION ON SOCIO-TECHNICAL ENVIRONMENT OF SOFTWARE DEVELOPMENT PROJECTS (2011) (0)
- Enabling a Programming Environment for an Experimental Ion Trap Quantum Testbed (2021) (0)
- Post Moore's Law Report (2018) (0)
- Benchmark Characterization for Experiment a 1 System Evaluation (2004) (0)
- Miss Path Speculative SchedulingFor High (2007) (0)
This paper list is powered by the following services:
Other Resources About Tom Conte
What Schools Are Affiliated With Tom Conte?
Tom Conte is affiliated with the following schools:
