Trevor Mudge | Academic Influence

Trevor Mudge's AcademicInfluence.com Rankings

Trevor Mudge

Computer Science

#2283

World Rank

#2379

Historical Rank

#1024

USA Rank

Computer Architecture

#17

World Rank

#17

Historical Rank

#14

USA Rank

Database

#1913

World Rank

#2008

Historical Rank

#466

USA Rank

computer-science Degrees

Trevor Mudge

Engineering

#2017

World Rank

#2834

Historical Rank

#700

USA Rank

Electrical Engineering

#604

World Rank

#665

Historical Rank

#183

USA Rank

engineering Degrees

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Computer Science
Engineering

Trevor Mudge's Degrees

PhD Computer Science Stanford University
Masters Computer Science Stanford University

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Why Is Trevor Mudge Influential?

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According to Wikipedia, Trevor Mudge is a computer scientist, academic and researcher. He is the Bredt Family Chair of Computer Science and Engineering, and Professor of Electrical Engineering and Computer Science at the University of Michigan.

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Trevor Mudge's Published Works

Number of citations in a given year to any of this author's works

Total number of citations to an author for the works they published in a given year. This highlights publication of the most important work(s) by the author

Published Works

MiBench: A free, commercially representative embedded benchmark suite (2001) (3720)
Razor: a low-power pipeline based on circuit-level timing speculation (2003) (1395)
Leakage Current: Moore's Law Meets Static Power (2003) (1259)
Drowsy caches: simple techniques for reducing leakage power (2002) (913)
Near-Threshold Computing: Reclaiming Moore's Law Through Energy Efficient Integrated Circuits (2010) (825)
Neurosurgeon: Collaborative Intelligence Between the Cloud and Mobile Edge (2017) (766)
Power: A First-Class Architectural Design Constraint (2001) (565)
Combined dynamic voltage scaling and adaptive body biasing for lower power microprocessors under dynamic workloads (2002) (494)
A self-tuning DVS processor using delay-error detection and correction (2005) (429)
Disaggregated memory for expansion and sharing in blade servers (2009) (387)
Trace-driven memory simulation: a survey (1997) (332)
A survey of multicore processors (2009) (306)
Dynamic voltage scaling on a low-power microprocessor (2001) (299)
Improving NAND Flash Based Disk Caches (2008) (266)
SODA: A Low-power Architecture For Software Radio (2006) (259)
Improving code density using compression techniques (1997) (255)
Automatic Performance Setting for Dynamic Voltage Scaling (2001) (239)
Understanding and Designing New Server Architectures for Emerging Warehouse-Computing Environments (2008) (237)
Recognizing Partially Occluded Parts (1985) (233)
A performance comparison of contemporary DRAM architectures (1999) (229)
Sirius: An Open End-to-End Voice and Vision Personal Assistant and Its Implications for Future Warehouse Scale Computers (2015) (225)
PicoServer: using 3D stacking technology to enable a compact energy efficient chip multiprocessor (2006) (219)
An Analytical Model (1996) (210)
Circuit and microarchitectural techniques for reducing cache leakage power (2004) (201)
The bi-mode branch predictor (1997) (199)
Architecture of a Hypercube Supercomputer (1986) (193)
Full-system analysis and characterization of interactive smartphone applications (2011) (184)
True Random Number Generator With a Metastability-Based Quality Control (2007) (183)
Making typical silicon matter with Razor (2004) (177)
Drowsy instruction caches. Leakage power reduction using dynamic voltage scaling and cache sub-bank prediction (2002) (174)
DjiNN and Tonic: DNN as a service and its implications for future warehouse scale computers (2015) (172)
The YAGS branch prediction scheme (1998) (170)
Opportunities and challenges for better than worst-case design (2005) (163)
A Microprocessor-based Hypercube Supercomputer (1986) (158)
Analysis of branch prediction via data compression (1996) (155)
Improving data cache performance by pre-executing instructions under a cache miss (1997) (154)
Yield-Driven Near-Threshold SRAM Design (2010) (148)
OuterSPACE: An Outer Product Based Sparse Matrix Multiplication Accelerator (2018) (146)
Design Tradeoffs For Software-managed Tlbs (1994) (146)
AnySP: Anytime Anywhere Anyway Signal Processing (2009) (144)
FlashCache: a NAND flash memory file cache for low power web servers (2006) (143)
Razor: circuit-level correction of timing errors for low-power operation (2004) (141)
Analysis and design of latch-controlled synchronous digital circuits (1990) (124)
Hypercube supercomputers (1989) (123)
A look at several memory management units, TLB-refill mechanisms, and page table organizations (1998) (120)
Flextream: Adaptive Compilation of Streaming Applications for Heterogeneous Architectures (2009) (117)
Multiple Bus Architectures (1987) (116)
Sources of error in full-system simulation (2014) (115)
CheckT/sub c/ and minT/sub c/: timing verification and optimal clocking of synchronous digital circuits (1990) (112)
Evolution of thread-level parallelism in desktop applications (2010) (111)
Virtual memory in contemporary microprocessors (1998) (111)
Correlation and Aliasing in Dynamic Branch Predictors (1996) (110)
A semi-Markov model for the performance of multiple-bus systems (1985) (110)
From SODA to scotch: The evolution of a wireless baseband processor (2008) (108)
Energy efficient near-threshold chip multi-processing (2007) (107)
Wrong-path instruction prefetching (1996) (103)
Vertigo: automatic performance-setting for Linux (2002) (102)
Instruction fetching: Coping with code bloat (1995) (100)
An Analytical Model for Designing Memory Hierarchies (1996) (98)
Author retrospective improving data cache performance by pre-executing instructions under a cache miss (1997) (97)
Vertigo: automatic performance-setting for Linux (2002) (96)
SODA: A High-Performance DSP Architecture for Software-Defined Radio (2007) (93)
Power: A First Class Design Constraint for Future Architecture and Automation (2000) (92)
Centip3De: A 3930DMIPS/W configurable near-threshold 3D stacked system with 64 ARM Cortex-M3 cores (2012) (91)
Sponge: portable stream programming on graphics engines (2011) (90)
Reliability modeling and management in dynamic microprocessor-based systems (2006) (90)
Toward real-time performance benchmarks for Ada (1986) (84)
Analysis of Multiple-Bus Interconnection Networks (1986) (82)
Virtual Memory: Issues of Implementation (1998) (82)
Swizzle-Switch Networks for Many-Core Systems (2012) (81)
Exploring DRAM organizations for energy-efficient and resilient exascale memories (2013) (80)
Software-managed address translation (1997) (79)
On-Chip Cache Device Scaling Limits and Effective Fault Repair Techniques in Future Nanoscale Technology (2007) (73)
Thread-level parallelism and interactive performance of desktop applications (2000) (72)
14.7 A 288µW programmable deep-learning processor with 270KB on-chip weight storage using non-uniform memory hierarchy for mobile intelligence (2017) (71)
Reducing code size with run-time decompression (2000) (68)
Reducing register ports using delayed write-back queues and operand pre-fetch (2003) (66)
The limits of instruction level parallelism in SPEC95 applications (1999) (64)
High-Performance DRAMs in Workstation Environments (2001) (64)
Proactive transaction scheduling for contention management (2009) (60)
A study of mobile device utilization (2015) (60)
Instruction prefetching using branch prediction information (1997) (58)
Reconfigurable energy efficient near threshold cache architectures (2008) (58)
The role of adaptivity in two-level adaptive branch prediction (1995) (54)
Evaluation of a high performance code compression method (1999) (54)
Scaling towards kilo-core processors with asymmetric high-radix topologies (2013) (52)
Multi-Mechanism Reliability Modeling and Management in Dynamic Systems (2008) (51)
Stream Compilation for Real-Time Embedded Multicore Systems (2009) (51)
Integrated 3D-stacked server designs for increasing physical density of key-value stores (2014) (50)
An Energy Efficient Parallel Architecture Using Near Threshold Operation (2007) (49)
Integrating NAND flash devices onto servers (2009) (49)
Optimal allocation of on-chip memory for multiple-API operating systems (1994) (48)
Mobile supercomputers (2004) (48)
A hybrid approach to offloading mobile image classification (2014) (48)
Process variation in near-threshold wide SIMD architectures (2012) (48)
Centip3De: A Cluster-Based NTC Architecture With 64 ARM Cortex-M3 Cores in 3D Stacked 130 nm CMOS (2013) (47)
Assessing the performance limits of parallelized near-threshold computing (2012) (47)
High-level design verification of microprocessors via error modeling (1998) (47)
High-level test generation for design verification of pipelined microprocessors (1999) (47)
A Parallel Genetic Algorithm for Multiobjective Microprocessor Design (1995) (46)
ChipLock: support for secure microarchitectures (2005) (46)
Single-V/sub DD/ and single-V/sub T/ super-drowsy techniques for low-leakage high-performance instruction caches (2004) (44)
Uniprocessor Virtual Memory without TLBs (2001) (43)
Total power-optimal pipelining and parallel processing under process variations in nanometer technology (2005) (43)
Monster : a tool for analyzing the interaction between operating systems and computer architectures (1992) (43)
The impact of signal transition time on path delay computation (1993) (43)
Proceedings of the 24th annual international symposium on Computer architecture (1997) (42)
Centip3De: A 64-Core, 3D Stacked Near-Threshold System (2012) (42)
Design and Implementation of Turbo Decoders for Software Defined Radio (2006) (41)
Translation And Execution Of Distributed ADA Programs: Is It Still ADA? (1987) (41)
Identification of critical paths in circuits with level-sensitive latches (1995) (41)
Challenges for architectural level power modeling (2002) (41)
Design tradeoffs for software-managed TLBs (1993) (40)
Code Compression for DSP (1998) (40)
Software Defined Radio - A High Performance Embedded Challenge (2005) (40)
Energy-Autonomous Wireless Communication for Millimeter-Scale Internet-of-Things Sensor Nodes (2016) (39)
How to fake 1000 registers (2005) (39)
Collection and Analysis of Microprocessor Design Errors (2000) (39)
PicoServer: Using 3D stacking technology to build energy efficient servers (2008) (38)
Sparse-TPU: adapting systolic arrays for sparse matrices (2020) (38)
Integrating superscalar processor components to implement register caching (2001) (38)
The Next Generation Challenge for Software Defined Radio (2007) (38)
Low-Energy Data Cache Using Sign Compression and Cache Line Bisection (2002) (37)
HIERARCHICAL CONTROL STRUCTURE USING SPECIAL PURPOSE PROCESSORS FOR THE CONTROL OF ROBOT ARMS. (1982) (37)
Object-Based Computing and the Ada Programming Language (1985) (36)
WarpPool: Sharing requests with inter-warp coalescing for throughput processors (2015) (36)
Reducing pipeline energy demands with local DVS and dynamic retiming (2004) (36)
Trap-driven simulation with Tapeworm II (1994) (35)
Performance optimization of pipelined primary cache (1992) (35)
MacroSS: macro-SIMDization of streaming applications (2010) (35)
A 2.3Gb/s fully integrated and synthesizable AES Rijndael core (2003) (34)
Challenges and Opportunities for Extremely Energy-Efficient Processors (2010) (34)
Leakage power optimization techniques for ultra deep sub-micron multi-level caches (2003) (34)
Synchronization of pipelines (1993) (32)
Probabilistic analysis of a crossbar switch (1982) (32)
Timing Issues in the Distributed Execution of Ada Programs (1987) (32)
SPEX: A Programming Language for Software Defined Radio (2006) (31)
Intrinsic Checkpointing: A Methodology for Decreasing Simulation Time Through Binary Modification (2005) (31)
The effect of speculative execution on cache performance (1994) (31)
WiBench: An open source kernel suite for benchmarking wireless systems (2013) (31)
1 A 2 . 9 TOPS / W Deep Convolutional Neural Network SoC in FD-SOI 28 nm for Intelligent Embedded Systems (2017) (31)
A Class of Cellular Architectures to Support Physical Design Automation (1984) (30)
Bloom Filter Guided Transaction Scheduling (2011) (30)
Diet SODA: A power-efficient processor for digital cameras (2010) (30)
Vision Algorithms for Hypercube Machines (1987) (30)
Design and Analysis of LDPC Decoders for Software Defined Radio (2007) (30)
The microarchitecture of a low power register file (2003) (30)
Range image segmentation and surface parameter extraction for 3-D object recognition of industrial parts (1987) (30)
RegLess: Just-in-Time Operand Staging for GPUs (2017) (30)
Using Ada as a programming language for robot-based manufacturing cells (1984) (28)
Hardware support for hiding cache latency (1993) (28)
Web latency reduction via client-side prefetching (2000) (28)
Yield-driven near-threshold SRAM design (2007) (28)
DDR2 and Low Latency Variants (2000) (28)
The store-load address table and speculative register promotion (2000) (28)
A Preliminary Investigation into Parallel Routing on a Hypercube Computer (1987) (27)
A 4.5Tb/s 3.4Tb/s/W 64×64 switch fabric with self-updating least-recently-granted priority and quality-of-service arbitration in 45nm CMOS (2012) (27)
A low power software-defined-radio baseband processor for the Internet of Things (2016) (27)
Efficient Recognition of Partially Visible Objects Using a Logarithmic Complexity Matching Technique (1989) (27)
A Low-Power DSP for Wireless Communications (2010) (27)
Performance Optimization of Pipelined Primary Caches (1992) (26)
Leakage Current Reduction in VLSI Systems (2002) (26)
Automatic generation of salient features for the recognition of partially occluded parts (1987) (25)
Performance Limits of Trace Caches (1999) (25)
Mobile Supercomputers for the Next-Generation Cell Phone (2010) (25)
Prodigy: Improving the Memory Latency of Data-Indirect Irregular Workloads Using Hardware-Software Co-Design (2021) (25)
Monte Carlo Photon Transport On Shared Memory and Distributed Memory Parallel Processors (1987) (24)
Error analysis for the support of robust voltage scaling (2005) (24)
A 1.07 Tbit/s 128×128 swizzle network for SIMD processors (2010) (24)
Hierarchical coarse-grained stream compilation for software defined radio (2007) (24)
On The Control of Mechanical Manipulators (1982) (23)
Hierarchical decomposition and simulation of manufacturing cells using Ada (1986) (23)
Using non-volatile memory to save energy in servers (2009) (23)
VIX: Virtual Input Crossbar for efficient switch allocation (2014) (22)
Some problems in distributing real-time Ada programs across machines (1985) (21)
The Need for Large Register Files in Integer Codes (2000) (21)
Designing Future Warehouse-Scale Computers for Sirius, an End-to-End Voice and Vision Personal Assistant (2016) (21)
Full-System Critical Path Analysis (2008) (21)
Instruction Level Timing Mechanisms for Accurate Real-Time Task Scheduling (1987) (21)
A study of Thread Level Parallelism on mobile devices (2014) (21)
Parallel branch and bound algorithms on hypercube multiprocessors (1989) (20)
PEPSC: A Power-Efficient Processor for Scientific Computing (2011) (20)
Microarchitectural power modeling techniques for deep sub-micron microprocessors (2004) (20)
A limits study of benefits from nanostore-based future data-centric system architectures (2012) (20)
IDtrace/spl minus/a tracing tool for i486 simulation (1994) (19)
Analysis of bus hierarchies for multiprocessors (1988) (19)
Cellular Image Processing Techniques for VLSI Circuit Layout Validation and Routing (1982) (19)
Resource allocation in a high clock rate microprocessor (1994) (19)
Limits to Branch Prediction (2000) (18)
The MIRV SimpleScalar/PISA Compiler (2000) (18)
Parallel Processing For Computer Vision (1982) (18)
Timing verification of sequential domino circuits (1996) (18)
The design of a microsupercomputer (1991) (18)
Overview of complementary GaAs technology for high-speed VLSI circuits (1998) (17)
Recognizing partially hidden objects (1985) (17)
Implementing a cache for a high-performance GaAs microprocessor (1991) (16)
A programmable Galois Field processor for the Internet of Things (2017) (16)
The Impact of Instruction Compression on I-cache Performance (1997) (16)
FITS: framework-based instruction-set tuning synthesis for embedded application specific processors (2004) (16)
Data dwarfs: Motivating a coverage set for future large data center workloads (2010) (15)
The New DRAM Interfaces: SDRAM, RDRAM and Variants (2000) (15)
A System Solution for High-Performance, Low Power SDR (2005) (15)
Multilevel optimization in the design of a high-performance GaAs microcomputer (1991) (15)
Transmuter: Bridging the Efficiency Gap using Memory and Dataflow Reconfiguration (2020) (15)
A 7.3 M Output Non-Zeros/J Sparse Matrix-Matrix Multiplication Accelerator using Memory Reconfiguration in 40 nm (2019) (14)
Memory Interference Models with Variable Connection Time (1984) (14)
Architecting an LTE base station with graphics processing units (2013) (14)
Near-threshold computing in FinFET technologies: Opportunities for improved voltage scalability (2016) (14)
SWIFT: A 2.1Tb/s 32×32 self-arbitrating manycore interconnect fabric (2011) (14)
Instruction Level Mechanisms for Accurate Real-time Task Scheduling (1986) (14)
Analyzing the scalability of SIMD for the next generation software defined radio (2008) (14)
Notes on Calculating Computer Performance (1995) (14)
Quantitative analysis and optimization techniques for on-chip cache leakage power (2005) (14)
DVS for on-chip bus designs based on timing error correction (2005) (14)
Near Threshold Computing : Overcoming Performance Degradation from Aggressive Voltage Scaling (2009) (14)
Connection between formulations of robot arm dynamics with applications to simulation and control (1981) (14)
Using Graphics Processing Units in an LTE Base Station (2015) (13)
VLSI IMPLEMENTATION OF A NUMERICAL PROCESSOR FOR ROBOTICS. (1981) (13)
A Self-Tuning Dynamic Voltage Scaled Processor Using Delay-Error Detection and Correction (2006) (13)
Hi-Rise: A High-Radix Switch for 3D Integration with Single-Cycle Arbitration (2014) (13)
Report on the panel: “how can computer architecture researchers avoid becoming the society for irreproducible results?” (1996) (13)
Timing verification of sequential dynamic circuits (1996) (13)
A 7.3 M Output Non-Zeros/J, 11.7 M Output Non-Zeros/GB Reconfigurable Sparse Matrix–Matrix Multiplication Accelerator (2020) (13)
A Customized Processor for Energy Efficient Scientific Computing (2012) (12)
Total leakage optimization strategies for multi-level caches (2005) (12)
Crosspoint Cache Architectures (1987) (12)
Mighty-morphing power-SIMD (2010) (12)
Strategic directions in computer architecture (1996) (12)
Gallium-arsenide process evaluation based on a RISC microprocessor example (1993) (11)
Limits of Parallelism and Boosting in Dim Silicon (2013) (11)
Complementary GaAs technology for a GHz microprocessor (1996) (11)
Advances and Insights into Parallel SAT Solving (11)
MEDICS: Ultra-portable processing for medical image reconstruction (2010) (11)
Instrumentation Tools (1995) (11)
The space problem (1990) (10)
Two-dimensional partially visible object recognition using efficient multidimensional range queries (1987) (10)
Flexible product code-based ECC schemes for MLC NAND Flash memories (2011) (10)
An Intrusion-Tolerant and Self-Recoverable Network Service System Using A Security Enhanced Chip Multiprocessor (2005) (10)
Unifying Robot Arm Control (1984) (10)
Low power interconnects for SIMD computers (2011) (10)
Customizing wide-SIMD architectures for H.264 (2009) (10)
A parameterized dataflow language extension for embedded streaming systems (2008) (10)
End-to-end performance forecasting: finding bottlenecks before they happen (2009) (10)
Impact of FinFET on Near-Threshold Voltage Scalability (2017) (10)
IMAGE CODING USING THE MULTIMICROPROCESSOR SYSTEM PASM. (1982) (10)
A 160000 transistor GaAs microprocessor (1993) (10)
Analyzing the Next Generation Software Defined Radio for Future Architectures (2011) (9)
Enhancing DRAM Self-Refresh for Idle Power Reduction (2016) (9)
Using Low Cost Erasure and Error Correction Schemes to Improve Reliability of Commodity DRAM Systems (2016) (9)
High radix self-arbitrating switch fabric with multiple arbitration schemes and quality of service (2012) (9)
Circuit-aware architectural simulation (2004) (9)
Server Designs for Warehouse-Computing Environments (2009) (9)
CoSPARSE: A Software and Hardware Reconfigurable SpMV Framework for Graph Analytics (2021) (9)
Smart Register Files for High-Performance Microprocessors (1999) (9)
Multilevel Optimization of Pipelined Caches (1997) (9)
Reevaluating Fast Dual-Voltage Power Rail Switching Circuitry (2012) (9)
A comparison of two pipeline organizations (1994) (9)
Systematic objective-driven computer architecture optimization (1995) (8)
Is Storage Hierarchy Dead? Co-located Compute-Storage NVRAM-based Architectures for Data-Centric Workloads (2010) (8)
Centip3De: a many-core prototype exploring 3D integration and near-threshold computing (2013) (8)
Efficient Data Center Architectures Using Non-Volatile Memory and Reliability Techniques (2011) (8)
Equivalence of two formulations for robot arm dynamics (1980) (8)
Software TLB management in OSF/1 and Mach 3.0 (1992) (8)
Ada on a hypercube (1989) (8)
E-ECC: Low Power Erasure and Error Correction Schemes for Increasing Reliability of Commodity DRAM Systems (2015) (8)
Improving the Reliability of MLC NAND Flash Memories Through Adaptive Data Refresh and Error Control Coding (2014) (8)
Optimal clocking of circular pipelines (1991) (8)
A microarchitectural performance evaluation of a 3.2 Gbyte/s microprocessor bus (1993) (8)
ISSCC 2017 / SESSION 14 / DEEP-LEARNING PROCESSORS / 14 . 7 14 . 7 A 288 μW Programmable Deep-Learning Processor with 270 KB On-Chip Weight Storage Using Non-Uniform Memory Hierarchy for Mobile Intelligence (2018) (8)
Power-performance trade-offs in nanometer-scale multi-level caches considering total leakage (2005) (8)
Kernel-Based Memory Simulation. (1994) (7)
An Approximate Queueing Model for Packet Switched Multistage Interconnection Networks (1982) (7)
A dual-processor solution for the MAC layer of a software defined radio terminal (2005) (7)
A Course Sequence in Microprocessor-Based Digital Systems Design (1981) (7)
Solutions to the n Queens problem using tasking in Ada (1986) (7)
GaAs RISC processors (1992) (7)
Comparison of two common pipeline structures (1996) (7)
Report for the NSF Workshop on Cross ‐ layer Power Optimization and Management (2012) (7)
Fast Software-managed Code Decompression (1999) (6)
RATT-ECC (2016) (6)
Analysis of hardware prefetching across virtual page boundaries (2007) (6)
Proceedings of the International Conference on Compilers, Architecture and Synthesis for Embedded Systems (2001) (6)
Code Compression for DSP CSE-TR-380-98 (1998) (6)
Rapid Prototyping & Evaluation of High-Performance Computers (1996) (6)
An Instruction Stream Compression Technique 1 (1996) (6)
When Homogeneous becomes Heterogeneous Wearout Aware Task Scheduling for Streaming Applications (2007) (6)
SOLVING THE BIN OF PARTS PROBLEM. (1986) (5)
Swizzle Switch: A self-arbitrating high-radix crossbar for NoC systems (2012) (5)
PicoServer - building a compact energy efficient multiprocessor (2008) (5)
High performance hypercube communications (1988) (5)
Units of distribution for distributed Ada (1987) (5)
Accelerating Deep Neural Network Computation on a Low Power Reconfigurable Architecture (2020) (5)
USING ADA AS A ROBOT SYSTEM PROGRAMMING LANGUAGE. (1983) (5)
Parallelization techniques for implementing trellis algorithms on graphics processors (2013) (5)
Checkpointing Exascale Memory Systems with Existing Memory Technologies (2016) (5)
A Verilog preprocessor for representing datapath components (1995) (5)
Sirius Implications for Future Warehouse-Scale Computers (2016) (5)
WIRE ROUTING EXPERIMENTS ON A RASTER PIPELINE SUBARRAY MACHINE. (1983) (5)
Reducing Idle Mode Power in Software Defined Radio Terminals (2006) (5)
Evaluating private vs. shared last-level caches for energy efficiency in asymmetric multi-cores (2014) (5)
PowerFITS: Reduce Dynamic and Static I-Cache Power Using Application Specific Instruction Set Synthesis (2005) (5)
Configurable-ECC: Architecting a Flexible ECC Scheme to Support Different Sized Accesses in High Bandwidth Memory Systems (2019) (4)
A Deep Dive Into Understanding The Random Walk-Based Temporal Graph Learning (2021) (4)
Reconfigurable Multicore Server Processors for Low Power Operation (2009) (4)
The specialization trend in computer hardware (2015) (4)
Cache coherence requirements for interprocess rendezvous (1990) (4)
Hierarchical decomposition and simulation of manufacturing cells (1984) (4)
Optimal Clocking of Synchronous Systems (2011) (4)
Exploiting large register files in general purpose code (2000) (4)
Accelerating Linear Algebra Kernels on a Massively Parallel Reconfigurable Architecture (2020) (4)
A Programmable Vector Coprocessor Architecture for Wireless Applications (2004) (4)
A load balancing technique for memory channels (2018) (4)
A high level simulator integrated with the Mirv compiler (1999) (4)
Duplicating and Verifying LogTM with OS Support in the M5 Simulator (2007) (4)
1 A 4 . 5 Tb / s 3 . 4 Tb / s / W 64 × 64 Switch Fabric with Self-Updating Least-Recently-Granted Priority and Quality-of-Service Arbitration in 45 nm CMOS (2018) (3)
Improving data cache performance by pre-executing instructions under a cache miss (2014) (3)
Multicore architectures (2007) (3)
OBJECT-BASED COMPUTER ARCHITECTURES. (1983) (3)
A Comment on "An Analytical Model for Designing Memory Hierarchies" (1997) (3)
Impact of MCMs on system performance optimization (1992) (3)
Teaching Assembly Language Programming with ZIP, a Z80 Assembly Language Interpreter Program (1983) (3)
Versa: A Dataflow-Centric Multiprocessor with 36 Systolic ARM Cortex-M4F Cores and a Reconfigurable Crossbar-Memory Hierarchy in 28nm (2021) (3)
Memory-interference model for multiprocessors based on semi-Markov processes (1987) (3)
SuiteSpecks and SuiteSpots: A methodology for the automatic conversion of benchmarking programs into intrinsically checkpointed assembly code (2009) (3)
Energy-Efficient Simultaneous Thread Fetch from Different Cache Levels in a Soft Real-Time SMT Processor (2008) (3)
An Analysis Of Hypercube Architectures For Image Pattern Recognition Algorithms (1987) (3)
EXPERIMENTS IN OCCLUDED PARTS RECOGNITION. (1984) (3)
The design of a GaAs micro-supercomputer (1991) (3)
Hierarchical Gate-Array Routing on a Hypercube Multiprocessor (1990) (3)
ADA IN A MANUFACTURING ENVIRONMENT. (1987) (3)
Comparisons between ADA and LISP (1985) (3)
Distributed Ada on a loosely coupled multiprocessor (1988) (3)
The trading function in action (1996) (3)
The time problem (1990) (3)
Performance of Parallel Loops using Alternative Cache Consistency Protocols on a Non-Bus Multiprocessor (1990) (3)
SPECIAL PURPOSE VLSI PROCESSORS FOR INDUSTRIAL ROBOTS. (1981) (2)
Guest editorial: Concurrent hardware and software design for multiprocessor SoC (2006) (2)
Distributed run-time support for Ada on the NCUBE hypercube mulitprocessor (1987) (2)
Efficiency of Feature Dependent Algorithms for the Parallel Processing of Images (1983) (2)
Low-Power Scientific Computing (2009) (2)
Accelerating Smith-Waterman Alignment Workload with Scalable Vector Computing (2017) (2)
Versa: A 36-Core Systolic Multiprocessor With Dynamically Reconfigurable Interconnect and Memory (2022) (2)
Determining the Pose of an Object (1986) (2)
Design and Performance Evaluation of Global History Dynamic Branch Predictors (1998) (2)
SMART: STT-MRAM architecture for smart activation and sensing (2019) (2)
Erratum: Circuit and microarchitectural techniques for reducing cache leakage power (IEEE Transactions on Very Large Scale Integration (VLSI) Systems (Feb. 2004) 12:2 (167-184)) (2005) (2)
A 507 GMACs/J 256-Core Domain Adaptive Systolic-Array-Processor for Wireless Communication and Linear-Algebra Kernels in 12nm FINFET (2022) (2)
Tagless Two-level Branch Prediction Schemes (2000) (2)
Design optimization for high-speed per-address two-level branch predictors (1997) (2)
Trap-driven memory simulation with Tapeworm II (1997) (2)
POWER ANALYZER FOR POCKET COMPUTING (PAPC) (2004) (2)
System Design For Local Neighborhood Processing (1985) (2)
Proceedings of the 28th Annual International Symposium on Microarchitecture, Ann Arbor, Michigan, USA, November 29 - December 1, 1995 (1995) (2)
Thread-level parallelism and interactive performance of desktop applications (2000) (2)
Hybrid Myths in Branch Prediction (2)
CASE STUDY OF A PROGRAM FOR THE RECOGNITION OF OCCLUDED PARTS. (1983) (2)
Special purpose architectures for computer vision (1982) (2)
XPoint cache: Scaling existing bus-based coherence protocols for 2D and 3D many-core systems (2012) (2)
Object-based computer systems and the Ada programming language (1983) (2)
Parallel language constructs for efficient parallel processing (1992) (2)
Modeling Domino Logic for Static Timing Analysis (1996) (2)
PicoServer Revisited: On the Profitability of Eliminating Intermediate Cache Levels (2012) (2)
Ada on hypercube (1988) (2)
Review of The structure of computers and computation Vol. I by David J. Kuck. John Wiley & and Sons 1978 (1980) (2)
User manual for ZIP : a Z80 assembly language interpreter program (1984) (1)
Evaluation of Design Error Models for Verification Testing of Microprocessors 1 (1998) (1)
Hardware/Software Transparency In Robotics Through Object Level Design (1983) (1)
SimpleDSP : A Fast and Flexible DSP Processor Model ( EXTENDED ABSTRACT ) (2003) (1)
EXtreme Virtual Pipelining (XVP): Moving Towards Scalable Multithreaded Processors (2005) (1)
Impact of Future Technologies on Architecture (2016) (1)
A queueing model of delta networks (1983) (1)
A complementary GaAs (CGaAs/sup TM/) 32-bit multiply accumulate unit (1997) (1)
Chapter 8 Architectural Techniques for Adaptive Computing (2008) (1)
VLSI crossbar design version two (1982) (1)
Lazy cache invalidation for self-modifying codes (2012) (1)
OVERCOMING MOORE ’ S CURSE : TECHNIQUES FOR POWERING LARGE TRANSISTOR COUNTS IN SUB-45 NM TECHNOLOGIES (2009) (1)
Faster Static Timing Analysis via Bus Compression (2000) (1)
HETSIM: Simulating Large-Scale Heterogeneous Systems using a Trace-driven, Synchronization and Dependency-Aware Framework (2020) (1)
Kernel-based memory simulation (extended abstract) (1994) (1)
Leverage Mobile GPUs for Flexible High-Speed Wireless Communication (2015) (1)
MirvKit A framework for compiler and computer architecture research (1998) (1)
A 7.3 M Output Non-Zeros/J Sparse Matrix-Matrix Multiplication Accelerator using Memory Reconfiguration in 40 nm (2019) (1)
Design of a High Level Intermediate Representation for Attribute-based Analysis (1998) (1)
Grand challenges in embedded systems (2005) (1)
A Complementary GaAs ( CGaAsT ” ) 32-bit Multiply Accumulate Unit (1998) (1)
Support for Nomadism in a Global Environment (1997) (1)
Architectural Techniques for Adaptive Computing (2008) (1)
Low Power Robust Computing (2004) (1)
MeNDA: a near-memory multi-way merge solution for sparse transposition and dataflows (2022) (1)
Thoughts on Winning the 2014 Eckert-Mauchly Award (2015) (1)
A High Performance GaAs Microprocessor (1993) (1)
TEACHING ASSEMBLY LANGUAGE USING AN ASSEMBLY LANGUAGE INTERPRETER. (1981) (1)
CoPTA: Contiguous Pattern Speculating TLB Architecture (2020) (1)
Computer Power : A First-Class Architectural Design Constraint (1)
CAD, Robot Programming and Ada (1984) (1)
On the Control of Mechanical Manipulator (1982) (1)
Efficient Encoding Of Local Shape: Features For 3-D Object Recognition (1989) (1)
Circuit design advances for ultra-low power sensing platforms (2010) (1)
Grand challenges in embedded systems (2005) (1)
Domain-Specific Architectures: Research Problems and Promising Approaches (2022) (1)
Special issue on compilers, architecture, and synthesis for embedded systems (2003) (0)
Performance and power analysis of computer systems (2005) (0)
Analysis of multistage networks with unique interconnection paths (1982) (0)
An investigation of the discrete Karhunen-Loeve transform : methods and computational aspects (1983) (0)
LATNECY REDUCTION VIA CLIENT-SIDE PREFETCHING (0)
Recognition, tracking, and pose estimation of arbitrarily shaped 3-D objects in cluttered intensity and range imagery (1991) (0)
Accelerating Graph Analytics on a Reconfigurable Architecture with a Data-Indirect Prefetcher (2023) (0)
Computer architecture instruction at the University of Michigan (1998) (0)
Taxonomy of benchmarks (1990) (0)
Squaring the circle: Executing Sparse Matrix Computations on FlexTPU---A TPU-Like Processor (2022) (0)
Proceedings of the International Conference on Compilers, Architectures and Synthesis for Embedded Systems, CASES 2002, Greenoble, France, October 8-11, 2002 (2002) (0)
Software-managed Address Translation 2 Memory System Requirements (0)
Server Designs for Warehouse- Computing Environments the Enormous Scale of Warehouse-computing Environments Leads to Unique Requirements in Which Cost and Power Figure Prominently. Models and Metrics Quantifying These Requirements, along with a Benchmark Suite to Capture Workload Behavior, Help Iden (2009) (0)
SEMANTRIX: a semantically guided digital electronic machine. (1973) (0)
A Case Study of a Hardware-Managed TLB in a Multi-Tasking Environment (2000) (0)
Using Graphics Processing Units in an LTE Base Station (2014) (0)
Improving the Reliability of MLC NAND Flash Memories Through Adaptive Data Refresh and Error Control Coding (2014) (0)
Thetrading functionin action (1996) (0)
Session details: Microarchitecture-level power analysis and optimization techniques (2005) (0)
Session details: Dynamic voltage scaling (2005) (0)
Measuring Process Migration Effects Using an MP Simulator (1992) (0)
CSE-TR-Faster Static Timing Analysis via Bus Compression (1996) (0)
CoDR: Computation and Data Reuse Aware CNN Accelerator (2021) (0)
Ada on a Hypercub e (0)
CHARACTERISTICS OF SOME AUGMENTED PETRI NETS. (1976) (0)
FITS : Framework-based Instruction-set Tuning Synthesis for Embedded Systems ( Extended Abstract ) (2004) (0)
An adaptive L2 cache prefetching mechanism for effective exploitation of abundant memory bandwidth of 3-D IC technology (2013) (0)
Technologies for reducing power (2010) (0)
ANALYSIS OF A MULTIPORT MEMORY. (1982) (0)
ADVANCED CONTROL FOR MULTIROBOT ASSEMBLY SYSTEMS. (1983) (0)
Program committee (2018) (0)
TAU 92 , March 92 Multiphase Retiming Using minTc 1 (2011) (0)
The Architecture of Smart Phones (2015) (0)
M icroarc h itect u ral Power MO ng Techniques for Deep Su b-Micron Microprocessors* (2004) (0)
Quality-of-service for a high-radix switch (2014) (0)
Error Simulation with Conditional Error Models (0)
A Self-Tuning DynamicVoltage Scaled Processor UsingDelay-Error Detection and Correction (2006) (0)
Architecture . Biotechnology computing (1993) (0)
GRACE: A Scalable Graph-Based Approach to Accelerating Recommendation Model Inference (2023) (0)
Introduction to the Special Section on Energy Efficient Computing (2005) (0)
Research into the architecture of CAD-based robot-vision systems. Final report, May 1984-31 October 1987 (1988) (0)
SMART (2019) (0)
I MPACT OF MCMÕ S ON H IGH P ERFORMANCE P ROCESSORS (1997) (0)
Timing Analysis of Domino Logic (1996) (0)
A Parallel Genetic Algorithm for Multiobjective Microprocessor Design 1 Microprocessor Design Problem (1995) (0)
1 DDR 2 and Low Latency Variants (2007) (0)
Fine-Grained Management of Thread Blocks for Irregular Applications (2019) (0)
Session details: Microarchitecural techniques for power reduction (2004) (0)
Design and Applications of a Virtual Context Architecture (2004) (0)
Sirius Web Extra (2016) (0)
Gaas Rlsc Processors (2004) (0)
NDMiner (2022) (0)
SERVER DESIGNS FOR WAREHOUSE (2009) (0)
A rationale for the design and implementation of Ada benchmark programs (1990) (0)
Energy-efficient computing for mobile signal processing (2011) (0)
Guest Editor's Introduction: Top Picks from the Computer Architecture Conferences of 2009 (2010) (0)
A common distributed language approach to software integration (1989) (0)
Timing Analysis of Digital Systems with Gated Clocks (1995) (0)
An algorithm for model based recognition of objects using range maps (1987) (0)
A Design Language for Modular Asynchronous Control Structures (1977) (0)
An ultra low power SIMD processor for wireless devices (2010) (0)
Message from the general chairs and the program chair (2007) (0)
A computer hardware design language for multiprocessor systems. (1977) (0)
Session details: Hot topic - low-power multi-core architectures (2005) (0)
A computer architecture for parallel processing (1978) (0)
A Case Stud y of a Har dware-Mana ged TLB in a Multi-T asking En vir onment (1994) (0)
Session details: 3D/caches (2009) (0)
The New D RAM Interfaces: SDRAM, D RDRAM a nd Variants (2000) (0)
Recommendations and future trends (1990) (0)
Memory Management Hardware, and its Support for Operating Systems (1997) (0)
A stochastic model of parallel and concurrent program execution on multiprocessors (1982) (0)
Session details: Power analysis for high-performance microprocessor design techniques (2010) (0)
Extremely energy-efficient processors (0)
Hot topic: low power multi-core architectures [Special Session] (2005) (0)
Improving Energy Efficiency of Convolutional Neural Networks on Multi-core Architectures through Run-time Reconfiguration (2022) (0)
Session details: Power modeling and optimization for embedded systems (2004) (0)
Rethinking DRAM's Page Mode With STT-MRAM (2023) (0)
Introduction to the Special Issue on Domain-Specific System-on-Chip Architectures and Run-Time Management Techniques (2023) (0)
Enabling Software-Defined RF Convergence with a Novel Coarse-Scale Heterogeneous Processor (2022) (0)
Mint: An Accelerator For Mining Temporal Motifs (2022) (0)
Bin of parts strategy (1982) (0)
5. Concluding Remarks 4.3 Breakdown of Misprediction for the Gshare and Bi-mode Schemes 4.4 Go Benchmark Table 4: Numbers of Changes between Different Bias Classes for the History-indexed and Bi-mode Schemes (1992) (0)
Compiler-Directed Instruction Stream Compression (1998) (0)
Chapter 6: Optimization (2018) (0)
Locality-Aware Optimizations for Improving Remote Memory Latency in Multi-GPU Systems (2022) (0)
Baseband Processing Architectures for SDR (2009) (0)
Parallel and distributed issues (1990) (0)
A memory rename table to reduce energy and improve performance (2014) (0)

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