Takehiro Sasao

Q: What Schools Are Affiliated With Takehiro Sasao

Takehiro Sasao is affiliated with the following schools: Meiji University, Kyushu Institute of Technology

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Takehiro Sasao

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Takehiro Sasao

Computer Science

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Engineering
Computer Science

Takehiro Sasao's Degrees

PhD Electrical Engineering Stanford University
Masters Electrical Engineering Stanford University
Bachelors Electrical Engineering Stanford University

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Takehiro Sasao's Published Works

Number of citations in a given year to any of this author's works

Total number of citations to an author for the works they published in a given year. This highlights publication of the most important work(s) by the author

Published Works

Switching Theory for Logic Synthesis (1999) (396)
Logic Synthesis and Optimization (1997) (290)
On the complexity of mod-2l sum PLA's (1990) (202)
Logic Synthesis and Verification (2013) (180)
EXMIN: a simplification algorithm for exclusive-OR-sum-of-products expressions for multiple-valued input two-valued output functions (1990) (155)
Input Variable Assignment and Output Phase Optimization of PLA's (1984) (144)
FPGA Design by Generalized Functional Decomposition (1993) (123)
And-Exor Expressions and their Optimization (1993) (101)
Memory-Based Logic Synthesis (2011) (89)
Multiple-Valued Decomposition of Generalized Boolean Functions and the Complexity of Programmable Logic Arrays (1981) (79)
Easily testable realizations for generalized Reed-Muller expressions (1994) (78)
A method to represent multiple-output switching functions by using multi-valued decision diagrams (1996) (70)
On the Optimal Design of Multiple-Valued PLA's (1989) (69)
Spectral Transform Decision Diagrams (1996) (66)
A cascade realization of multiple-output function for reconfigurable hardware (2001) (65)
Representations of Logic Functions Using EXOR Operators (1996) (65)
Selection of potentially testable path delay faults for test generation (2000) (64)
Numerical Function Generators Using LUT Cascades (2007) (61)
Average path length of binary decision diagrams (2005) (60)
Easily Testable Sequential Machines with Extra Inputs (1975) (56)
Representations of Discrete Functions (2011) (55)
Ternary decision diagrams. Survey (1997) (54)
A design method for look-up table type FPGA by pseudo-Kronecker expansion (1994) (53)
A deep convolutional neural network based on nested residue number system (2015) (52)
Two-level logic minimization (2001) (49)
A method to decompose multiple-output logic functions (2003) (48)
On the optimization of heterogeneous MDDs (2005) (47)
An application of multiple-valued logic to a design of programmable logic arrays (1978) (45)
Compact representations of logic functions using heterogeneous MDDs (2003) (44)
A heuristic algorithm to design AND-OR-EXOR three-level networks (1998) (44)
Multiple-valued logic and optimization of programmable logic arrays (1988) (43)
Optimization of multiple-valued AND-EXOR expressions using multiple-place decision diagrams (1992) (40)
Conservative Logic Elements and Their Universality (1979) (39)
Linear decomposition of index generation functions (2012) (38)
Minimization of AND-EXOR Expressions Using Rewrite Rules (1993) (38)
A Design Method for AND-OR-EXOR Three-Level Networks (1995) (38)
On the numbers of variables to represent sparse logic functions (2008) (36)
Index Generation Functions: Recent Developments (2011) (36)
DECOMPOS : An integrated system for functional decomposition (1998) (36)
Efficient computation of canonical form for boolean matching in large libraries (2004) (36)
Design Methods for Multiple-Valued Input Address Generators (2006) (35)
On the number of segments needed in a piecewise linear approximation (2010) (35)
Unified algorithm to generate Walsh functions in four different orderings and its programmable hardware implementations (2005) (34)
MACDAS: Multi-level AND-OR Circuit Synthesis Using Two-Variable Function Generators (1986) (33)
An Algorithm to Derive the Complement of a Binary Function with Multiple-Valued Inputs (1985) (32)
Large-scale SOP minimization using decomposition and functional properties (2003) (32)
On LUT cascade realizations of FIR filters (2005) (32)
Worst and Best Irredundant Sum-of-Products Expressions (2001) (31)
An FPGA design of AES encryption circuit with 128-bit keys (2005) (31)
Logic Synthesis with Exor Gates (1993) (31)
A hardware simulation engine based on decision diagrams (2000) (30)
Minimization of Average Path Length in BDDs by Variable Reordering (2003) (30)
A transformation of multiple-valued input two-valued output functions and its application to simplification of exclusive-or sum-of-products expressions (1991) (30)
Application of multiple-valued logic to a serial decomposition of PLAs (1989) (30)
Ternary Decision Diagrams and their Applications (1996) (29)
On the number of dependent variables for incompletely specified multiple-valued functions (2000) (28)
Planar multiple-valued decision diagrams (1995) (28)
Multiple-valued minimization to optimize PLAs with output EXOR gates (1999) (27)
Encoding of Boolean Functions and its Application to LUT Cascade Synthesis (2002) (27)
Note on nutation in ephemerides. (1979) (27)
Compact SOP representations for multiple-output functions-an encoding method using multiple-valued logic (2001) (26)
On Bi-Decompositions of Logic Functions (1997) (26)
GRMIN2: A heuristic simplification algorithm for generalised Reed-Muller expressions (1996) (26)
A Design of AES Encryption Circuit with 128-bit Keys Using Look-Up Table Ring on FPGA (2006) (25)
Multi-Level Logic Synthesis (1999) (24)
Calculation of Reed-Muller-Fourier coefficients of multiple-valued functions through multiple-place decision diagrams (1994) (24)
Application of LUT cascades to numerical function generators (2004) (24)
Evaluation of multiple-output logic functions using decision diagrams (2003) (24)
Minimization of AND-OR-EXOR Three-Level Networks with AND Gate Sharing (Special Issue on Synthesis and Verification of Hardware Design) (1997) (24)
On the Complexity of Classification Functions (2008) (23)
An Implementation of an Address Generator Using Hash Memories (2007) (23)
On the Number of Fanout-Free Functions and Unate Cascade Functions (1979) (23)
Comparison of Decision Diagrams for Multiple-Output Logic Functions (2002) (23)
Implementation of Multiple-Valued CAM Functions by LUT Cascades (2006) (22)
A Random Forest Using a Multi-valued Decision Diagram on an FPGA (2017) (21)
Approach to design a compact reversible low power binary comparator (2014) (21)
A memory-based realization of a binarized deep convolutional neural network (2016) (21)
On the Minimization of Longest Path Length for Decision Diagrams (2004) (21)
Decision diagrams for discrete functions: classification and unified interpretation (1998) (21)
A Reduction Method for the Number of Variables to Represent Index Generation Functions: s-Min Method (2015) (21)
Programmable numerical function generators based on quadratic approximation: architecture and synthesis method (2006) (21)
Fast Hardware Computation of x Mod z (2011) (21)
Radix converters: complexity and implementation by LUT cascades (2005) (20)
Implementation of multiple-output functions using PQMDDs (2000) (20)
Hahoe KAIST Robot Theatre: learning rules of interactive robot behavior as a multiple-valued logic synthesis problem (2005) (20)
Realization of multiple-output functions by reconfigurable cascades (2001) (20)
An optimization of AND-OR-EXOR three-level networks (1997) (20)
A Regular Expression Matching Circuit Based on a Decomposed Automaton (2011) (20)
Fast Boolean matching under permutation using representative (1999) (19)
BDD representation for incompletely specified multiple-output logic functions and its applications to functional decomposition (2005) (19)
A New Expansion of Symmetric Functions and Their Application to Non-Disjoint Functional Decompositions for LUT Type FPGAs (2000) (19)
Exact Minimization of FPRMs Using Multi-Terminal Exor TDDs (1996) (19)
On the Complexity of Three-Level Logic Circuits(Complexity Theory and Related Topics) (1990) (19)
Analysis and synthesis of weighted-sum functions (2006) (18)
On the adders with minimum tests (1997) (18)
Compact BDD Representations for Multiple-Output Functions and Their Application (2001) (18)
A discussion on the history of research in arithmetic andReed-Muller expressions (2001) (18)
Complexities of Graph-Based Representations for Elementary Functions (2009) (18)
Progress in Applications of Boolean Functions (2010) (17)
Totally undecomposable functions: applications to efficient multiple-valued decompositions (1999) (17)
On Magnetic Bubble Logic Circuits (1976) (16)
A High-speed Low-power Deep Neural Network on an FPGA based on the Nested RNS: Applied to an Object Detector (2018) (16)
Multi-level Logic Synthesis Based on Pseudo-Kronecker Decision Diagrams and Local Transformation (1995) (16)
Realization of sequential circuits by look-up table rings (2004) (16)
Ferrite plating of Fe/sub 3/O/sub 4/ and Fe/sub 3-x/Ni/sub x/O/sub 4/ films at 100-200 degrees C (1989) (16)
A Design Method of Address Generators Using Hash Memories (2006) (16)
Fast Boolean matching under permutation by efficient computation of canonical form (2004) (16)
Representations of Elementary Functions Using Binary Moment Diagrams (2006) (15)
On bi-decomposition of logic functions (1997) (15)
Programmable numerical function generators: architectures and synthesis method (2005) (15)
The Parallel Sieve Method for a Virus Scanning Engine (2009) (15)
Representations of Elementary Functions Using Edge-Valued MDDs (2007) (15)
A Method to Find Linear Decompositions for Incompletely Specified Index Generation Functions Using Difference Matrix (2014) (15)
HART: A hardware for logic minimization and verification (1985) (15)
Programmable logic device with an 8-stage cascade of 64K-bit asynchronous SRAMs (2005) (14)
Shared Multi-Terminal Binary Decision Diagrams for Multiple-Output Functions (Special Section on VLSI Design and CAD Algorithms) (1998) (14)
An exact minimization algorithm for generalized Reed-Muller expressions (1994) (14)
An algorithm to find optimum support-reducing decompositions for index generation functions (2017) (14)
Representation of Incompletely Specified Index Generation Functions Using Minimal Number of Compound Variables (2009) (14)
Analysis of Multi-state Systems with Multi-state Components Using EVMDDs (2012) (14)
A Lower Bound on the Number of Variables to Represent Incompletely Specified Index Generation Functions (2014) (14)
A Comparison of Architectures for Various Decision Diagram Machines (2010) (13)
Comparison of the worst and best sum-of-products expressions for multiple-valued functions (1997) (13)
On the average path length in decision diagrams of multiple-valued functions (2003) (13)
On properties of Kleene TDDs (1997) (13)
Average an Worst Case Number of Nodes in Decision Diagrams of Symmetric Multiple-Valued Functions (1997) (13)
Row-shift decompositions for index generation functions (2012) (13)
Compact Numerical Function Generators Based on Quadratic Approximation: Architecture and Synthesis Method (2006) (13)
Implementation of Walsh function generator of order 64 using LUT cascades (2004) (13)
Optimization Methods in Look-Up Table Rings (2004) (13)
Index Generation Functions: Minimization Methods (2017) (12)
GRMIN: a heuristic simplification algorithm for generalized Reed-Muller expressions (1995) (12)
Index Generation Functions: Tutorial (2014) (12)
The Eigenfunction of the Reed-Muller transformation (2007) (11)
Efficient Computation of Canonical Form under Variable Permutation and Negation for Boolean Matching in Large Libraries (2006) (11)
BDD Representation for Incompletely Specified Multiple-Output Logic Functions and Its Applications to the Design of LUT Cascades (2007) (11)
Output Phase Optimization for AND-OR-EXOR PLAs with Decoders and Its Application to Design of Adders (2005) (11)
A Comparison of Heterogeneous Multi-valued Decision Diagram Machines for Multiple-Output Logic Functions (2011) (11)
A Realization of Index Generation Functions Using Modules of Uniform Sizes (2010) (11)
A Packet Classifier Using a Parallel Branching Program Machine (2010) (11)
An Efficient Heuristic for Linear Decomposition of Index Generation Functions (2016) (11)
On the properties of multiple-valued functions that are symmetric in both variable values and labels (1998) (11)
Optimization of Pseudo-Kronecker Expressions Using Multiple-Place Decision Diagrams (1993) (10)
Bounds on the Average Number of Products in the Minimum Sum-of-Products Expressions for Multiple-Valued Input Two-Valued Output Functions (1991) (10)
On the Numbers of Variables to Represent Multi-valued Incompletely Specified Functions (2010) (10)
Or-and-Or Three-Level Networks (1996) (10)
Multiple-Valued Input Index Generation Functions: Optimization by Linear Transformation (2012) (10)
Average Path Length as a Paradigm for the Fast Evaluation of Functions Represented by Binary Decision Diagrams (2002) (10)
An exact minimization of AND-EXOR expressions using reduced covering functions (1994) (10)
Heuristics to Minimize Multiple-Valued Decision Diagrams (2000) (10)
Design Method for Numerical Function Generators Based on Polynomial Approximation for FPGA Implementation (2007) (10)
Design of multiple-output networks using time domain multiplexing and shared multi-terminal multiple-valued decision diagrams (1998) (10)
Area-Time Complexities of Multi-Valued Decision Diagrams (2004) (10)
Exact and Heuristic Minimization of the Average Path Length in Decision Diagrams (2005) (10)
A Design Algorithm for Sequential Circuits Using LUT Rings (2005) (10)
Generalized Reed-Muller Expressions: Complexity and an Exact Minimization Algorithm (Special Section on VLSI Design and CAD Algorithms) (1996) (9)
Soft-error tolerant TCAMs for high-reliability packet classifications (2014) (9)
A PC-Based Logic Simulator Using a Look-Up Table Cascade Emulator (2006) (9)
Exact minimization of fixed polarity Reed-Muller expressions for incompletely specified functions (2000) (9)
Index Generation Functions (2019) (9)
Input VariableAssignment andOutput PhaseOptimization ofPLA's (1984) (9)
Representations of logic functions using QRMDDs (2002) (9)
Design Method for Numerical Function Generators Using Recursive Segmentation and EVBDDs (2007) (9)
A CAM Emulator Using Look-Up Table Cascades (2007) (9)
A regular expression matching using non-deterministic finite automaton (2010) (9)
On Designs of Radix Converters Using Arithmetic Decompositions--Binary to Decimal Converters-- (2006) (9)
Three parameters to find functional decompositions (2000) (9)
A Quaternary Decision Diagram Machine and the Optimization of its Code (2009) (9)
A Systematic Design Method for Two-Variable Numeric Function Generators Using Multiple-Valued Decision Diagrams (2010) (9)
A Memory-Based IPv6 Lookup Architecture Using Parallel Index Generation Units (2015) (8)
A Unifying Approach to Edge-valued and Arithmetic Transform Decision Diagrams (2002) (8)
Shared multiple-valued decision diagrams for multiple-output functions (1999) (8)
Cascade realizations of two-valued input multiple-valued output functions using decomposition of group functions (2003) (8)
Planar Decision Diagrams for Multiple-Valued Functions (1996) (8)
Realization of regular ternary logic functions using double-rail logic (1999) (8)
A virus scanning engine using a parallel finite-input memory machine and MPUs (2009) (8)
Index to Constant Weight Codeword Converter (2011) (8)
A Parallel Branching Program Machine for Sequential Circuits: Implementation and Evaluation (2010) (8)
Distance Duality on Some Classes of Boolean Functions (2016) (8)
On the minimization of SOPs for bi-decomposition functions (2001) (8)
LUT cascades and emulators for realizations of logic functions (2005) (7)
Design Methods for Multi-Rail Cascades (2002) (7)
An Application of Autocorrelation Functions to Find Linear Decompositions for Incompletely Specified Index Generation Functions (2013) (7)
Representations of multiple-output switching functions using multiple-valued pseudo-Kronecker decision diagrams (2000) (7)
Programmable Architectures and Design Methods for Two-Variable Numeric Function Generators (2010) (7)
Four-variable AND-EXOR minimum expressions and their properties (1992) (7)
A fast segmentation algorithm for piecewise polynomial numeric function generators (2011) (7)
Exact Minimization of FPRMs for Incompletely Specified Functions by Using MTBDDs (2005) (7)
A packet classifier using LUT cascades based on EVMDDS (k) (2013) (7)
LUT Cascades Based on Edge-Valued Multi-Valued Decision Diagrams: Application to Packet Classification (2016) (7)
Cascade Realization of 3-Input 3-Output Conservative Logic Circuits (1978) (6)
A Method to Detect Bit Flips in a Soft-Error Resilient TCAM (2018) (6)
On the minimization of average path lengths for heterogeneous MDDs [multi-valued decision diagrams] (2004) (6)
A Realization of Multiple-Output Functions by a Look-Up Table Ring (2004) (6)
Redundant Multiple-Valued Number Systems (1997) (6)
On a wideband fast fourier transform for a radio telescope (2012) (6)
A Design Method of a Regular Expression Matching Circuit Based on Decomposed Automaton (2012) (6)
Implementations of Reconfigurable Logic Arrays on FPGAs (2007) (6)
An Exact Optimization Algorithm for Linear Decomposition of Index Generation Functions (2017) (6)
Bi-Partition of Shared Binary Decision Diagrams (2002) (6)
Applications of Zero-Suppressed Decision Diagrams (2014) (6)
Hardware Index to Permutation Converter (2012) (6)
Logic functions for cryptography - A tutorial (2009) (6)
Minimization of memory size for heterogeneous MDDs (2004) (6)
On the design of LPM address generators using multiple LUT cascades on FPGAs (2007) (6)
Fault Diagnosis for RAMs Using Walsh Spectrum (2004) (6)
Exploring Multi-Valued Minimization Using Binary Methods (2003) (6)
Numerical Function Generators Using Edge-Valued Binary Decision Diagrams (2007) (5)
On a Wideband Fast Fourier Transform Using Piecewise Linear Approximations: Application to a Radio Telescope Spectrometer (2012) (5)
Realization of Minimum Circuits with Two-Input Conservative Logic Elements (1978) (5)
A Comparison of Multi-Valued and Heterogeneous Decision Diagram Machines (2012) (5)
Design of Address Generators Using Multiple LUT Cascade on FPGA (2006) (5)
Representations of Multiple-Output Functions Using Binary Decision Diagrams for Characteristic Functions (Special Section on VLSI Design and CAD Algorithms) (1999) (5)
Average number of nodes in binary decision diagrams of Fibonacci func tions (1996) (5)
High-Speed Hardware Partition Generation (2015) (5)
Representation of Incompletely Specified Switching Functions Using Pseudo-Kronecker Decision Diagrams (2001) (5)
An Exact Optimization Method Using ZDDs for Linear Decomposition of Index Generation Functions (2018) (5)
An Architecture for IPv6 Lookup Using Parallel Index Generation Units (2013) (5)
A Realization of Index Generation Functions Using Multiple IGUs (2016) (5)
A fast logic simulator using a look up table cascade emulator (2006) (5)
Floating-Point Numerical Function Generators Using EVMDDs for Monotone Elementary Functions (2009) (5)
A regular expression matching circuit: Decomposed non-deterministic realization with prefix sharing and multi-character transition (2012) (5)
Time-Division Multiplexing Realizations of Multiple-Output Functions Based on Shared Multi-Terminal Multiple-Valued Decision Diagrams (1999) (5)
A Parallel Branching Program Machine for Emulation of Sequential Circuits (2009) (4)
Multiple-Valued Index Generation Functions: Reduction of Variables by Linear Transformation (2013) (4)
Design of Radix Converters Using Arithmetic Decomposition (2006) (4)
Multi-terminal Multi-valued Decision Diagrams for Characteristic Function Representing Cluster Decomposition (2012) (4)
Functional Decompositions Using an Automatic Test Pattern Generator and a Logic Simulator (1999) (4)
A Dynamic Programming Based Method for Optimum Linear Decomposition of Index Generation Functions (2019) (4)
An Update Method for a CAM Emulator Using an LUT Cascade Based on an EVMDD (K) (2014) (4)
Minimization of Average Path Lengths for Heterogeneous MDDs (2003) (4)
On the Numbers of Products in Prefix SOPs for Interval Functions (2013) (4)
Chandler wobble and viscosity in the Earth's core (1975) (4)
A TCAM generator for packet classification (2013) (4)
A method to evaluate logic functions in the presence of unknown inputs using LUT cascades (2004) (4)
Exact Minimization of AND - EXOR Expressions using Multi - terminal EXOR Ternary Decision Diagrams. (1995) (4)
Hardware to compute Walsh coefficients (2005) (4)
Programmable Numerical Function Generators for Two-Variable Functions (2008) (4)
On the minimization of SOPs for bi-decomposable functions (2001) (4)
An FFT Circuit for a Spectrometer of a Radio Telescope using the Nested RNS including the Constant Division (2017) (4)
Numeric Function Generators Using Piecewise Arithmetic Expressions (2011) (4)
Decomposition of Index Generation Functions Using a Monte Carlo Method (2018) (4)
EVMDD-Based Analysis and Diagnosis Methods of Multi-State Systems with Multi-State Components (2014) (4)
Representations of Two-Variable Elementary Functions Using EVMDDs and their Applications to Function Generators (2008) (4)
Planarity in ROMDDs of multiple-valued symmetric functions (1996) (4)
LP Characteristic Vector for Logic Functions (1993) (4)
On the Complexity of Some Classes of AND-EXOR Expressions (1992) (4)
Logic Synthesis of LUT Cascades with Limited Rails : A Direct Implementation of Multi-Output Functions (2002) (3)
An Exact Optimization Method using ZDDs for Linear Decomposition of Symmetric Index Generation Functions (2018) (3)
Logic Design Method for VLSI : Design and Test for Programmable Logic Arrays (1987) (3)
A soft-error tolerant TCAM using partial don't-care keys (2015) (3)
Publications in the First Twenty Years of Switching Theory and Logic Design (2001) (3)
A Virus Scanning Engine Using an MPU and an IGU Based on Row-Shift Decomposition (2013) (3)
Minimization of the Number of Edges in an EVMDD by Variable Grouping for Fast Analysis of Multi-State Systems (2013) (3)
A Low-Cost and High-Performance Virus Scanning Engine Using a Binary CAM Emulator and an MPU (2012) (3)
A Memory-Based Programmable Logic Device Using Look-Up Table Cascade with Synchronous Static Random Access Memories (2006) (3)
A Fast Updatable Implementation of Index Generation Functions Using Multiple IGUs (2017) (3)
On a Minimization of Variables to Represent Sparse Multi-Valued Input Decision Functions (2019) (3)
Head-Tail Expressions for Interval Functions (2014) (3)
A Balanced Decision Tree Based Heuristic for Linear Decomposition of Index Generation Functions (2017) (3)
Implementation of LPM Address Generators on FPGAs (2006) (3)
A minimization method for AND-EXOR expression using lower bound theorem (1993) (3)
An RNS FFT Circuit Using LUT Cascades Based on a Modulo EVMDD (2015) (3)
LUTMIN : FPGA Logic Synthesis with MUX-Based and Cascade Realizations (2009) (3)
A simplification method for AND-EXOR expressions for multiple-output functions (1996) (3)
On a Method to Reduce the Number of LUTs in LUT cascades (2001) (3)
Numerical function generators using bilinear interpolation (2008) (3)
On Optimum Linear Decomposition of Symmetric Index Generation Functions (2020) (3)
Analysis Methods of Multi-state Systems Partially Having Dependent Components Using Multiple-Valued Decision Diagrams (2014) (3)
Design Methods of Radix Converters Using Arithmetic Decompositions (2007) (3)
Multiple-valued combinational circuits with feedback (1994) (3)
A Linear Decomposition of Index Generation Functions: Optimization Using Autocorrelation Functions (2017) (3)
Hardware Index to Set Partition Converter (2013) (2)
Index generation functions: Theory and applications (2010) (2)
Analysis of the Number of Variables to Represent Index Generation Functions (2017) (2)
Inadmissible Class of Boolean Functions under Stuck-at Faults (2013) (2)
A Quaternary Decision Diagram Machine: Optimization of Its Code (2010) (2)
Reduction of the Number of Variables (2011) (2)
Four Decades of Multi-Valued Logic: Lists of Highly Cited Papers (2013) (2)
On decomposition of Kleene TDDs (1997) (2)
Floating-Point Numeric Function Generators Based on Piecewise-Split EVMDDs (2010) (2)
On the Number of Products to Represent Interval Functions by SOPs with Four-Valued Variables (2010) (2)
On Optimizations of Edge-Valued MDDs for Fast Analysis of Multi-State Systems (2014) (2)
On the Minimization of Variables to Represent Partially Defined Classification Functions (2020) (2)
An Application of 16-Valued Logic to Design of Reconfigurable Logic Arrays (2007) (2)
A Fast Head-Tail Expression Generator for TCAM -- Application to Packet Classification (2012) (2)
Use of Machine Learning Based on Constructive Induction in Dialogs with Robotic Heads (2003) (2)
A Low Power-Delay Product Processor Using Multi-valued Decision Diagram Machine (2012) (2)
On the Complexity of Error Detection Functions for Redundant Residue Number Systems (2008) (2)
Fast constant weight codeword to index converter (2011) (2)
Arithmetic Ternary Decision Diagrams Applications and Complexity (1999) (2)
Multiple-Bit-Flip Detection Scheme for a Soft-Error Resilient TCAM (2016) (2)
Cascade realization 3-input 3-output conservative logic circuits — application of three-valued logic to two-valued logic — (1976) (2)
On a Memory-Based Realization of Sparse Multiple-Valued Functions (2018) (2)
Combinatorial Computing-One Object Per Clock (2013) (2)
Lattice and Boolean Algebra (1999) (1)
On a prefetching heterogeneous MDD machine (2011) (1)
A Packet Classifier Based on Prefetching EVMDD (k) Machines (2014) (1)
FPGA Design using Pseudo-Kronecker Decision Diagrams (2000) (1)
History of Switching Theory (1999) (1)
Multi-Valued Input Two-Valued Output Function (1999) (1)
An Exact Method to Enumerate Decomposition Charts for Index Generation Functions (2018) (1)
On the Proportion of Digits in Redundant Numeration Systems (1996) (1)
On the ellipticity of the nearly diurnal polar motion. (1975) (1)
On a Realization of Multi-terminal Universal Interconnection Networks using Contact Switches (2020) (1)
Maximally Asymmetric Multiple-Valued Functions (2019) (1)
A simplification algorithm for logical expressions A5 (1983) (1)
VERA (VLBI for the Earth Rotation Study and Astrometry). (1988) (1)
A Design Method for Irredundant Cascades (2002) (1)
A New Equivalence Relation of Logic Functions and Its Application in the Design of AND-OR-EXOR Networks (2007) (1)
An Efficient Heuristic Algorithm for Linear Decomposition of Index Generation Functions (2015) (1)
Localization Method of Autonomous Moving Robot for Forest Industry (2017) (1)
Signal Processing and System Design of Cylinder Reliability Test for ISO Standard (2010) (1)
A fast method to derive minimum SOPs for decomposable functions (2004) (1)
Handwritten Digit Recognition Based on Classification Functions (2020) (1)
Edge Reduction for EVMDDs to Speed Up Analysis of Multi-state Systems (2015) (1)
Technologies for mm and Sub-mm VLBI: Multi-frequency Feed as a Tool for mm-Wave VLBI (2003) (1)
A Soft Error Tolerant LUT Cascade Emulator (2006) (1)
A Packet Classifier Using Parallel EVMDD (k) Machine (2013) (1)
A Method to Realize Logic Functions using LUTs and OR Gates (2003) (1)
Realizing all Index Generation Functions by the Row-Shift Method (2019) (1)
A Memory-Based Programmable Logic Device Using a Look-Up Table Cascade with Synchronous SRAMs (2005) (1)
3 Architecture for Numerical Function Generator 3 . 1 Overview (2004) (0)
On the Inadmissible Class of Multiple-Valued Faulty-Functions under Stuck-at Faults (2016) (0)
Logic Design Using Modules (1999) (0)
Sum-of-Generalized Products Expressions Applications and Minimization (2007) (0)
Properties of Multiple-Valued Partition Functions (2020) (0)
An evaluation system for logic functions based on decision diagrams (2004) (0)
MUX-Based Synthesis (2011) (0)
A Machine to Evaluate Decomposed Multi-Terminal Multi-Valued Decision Diagrams for Characteristic Functions (2013) (0)
A Realization of Cycle-based Simulation Engine using Decision Diagrams (1999) (0)
Improvement in the Quality of Solutions of a Heuristic Linear Decomposer for Index Generation Functions (2021) (0)
High-Speed Constant Weight Codeword Generators (2011) (0)
On Decision Diagrams for Maximally Asymmetric Functions (2022) (0)
An FFT Circuit Using Nested RNS in a Digital Spectrometer for a Radio Telescope (2016) (0)
Logic Design Using Exors (1999) (0)
Delay and Asynchronous Behavior (1999) (0)
2011 41st IEEE International Symposium on Multiple-Valued Logic (2011) (0)
C-Measure of Sparse Functions (2011) (0)
TK-2-2 MEMORY-BASED PROGRAMMABLE LOGIC ELEMENTS and THEIR APPLICATIONS (2008) (0)
Logic Functions with Various Properties (1999) (0)
キーワード QRMDD , メモリパッキング A Method to Evaluate Logic Functions Based On Decison Diagram Using Memory Packing (2007) (0)
A Design Method for Multiclass Classifiers (2021) (0)
Optimization of and-or Two-Level Logic Networks (1999) (0)
Symposium Committees (2015) (0)
Realization of Multi-Terminal Universal Interconnection Networks Using Contact Switches (2021) (0)
11 FPGA DESIGN BY GENERALIZED FUNCTIONAL DECOMPOSITION Tsutomu SASAO (0)
A Dynamically Reconfigurable Mixed Analog-Digital Filter Bank (2015) (0)
On a Decomposed MTMDDs for CF Machine (2012) (0)
Development of Self-Localization System in the Mountain Forest for Field Robot (2017) (0)
4-2 A Programmable Logic Circuit for Pattern Matching and Its Design Methods(4. New Attempts to the Next Generation of the System LSI, Analysis and Prospects of the System LSI over the Turning Point) (2013) (0)
A Logic Simulation using an Look-Up Table Cascade Emulator (2005) (0)
Complexity of Logic Networks (1999) (0)
Text CAM 4 IGU ( ) MPU IRQ ( ) FIFO FIFO Match index (2011) (0)
Remarks on the Design of First Digital Computers in Japan - Contributions of Yasuo Komamiya (2019) (0)
An Encoding Method for Rail Outputs in LUT cascades (2004) (0)
Realization of Regular Ternary Logic Functions. (1999) (0)
Evaluation of Logic Functions Using Hardware in the Presence of Unknown Inputs (1999) (0)
LUT カスケード A Method of Design and Update for An Address Generator Using a Hybrid Method (2007) (0)
A CAM Emulator UsingLook-UpTableCascades (2007) (0)
Classification Functions for Handwritten Digit Recognition (2021) (0)
On the Number of Variables To Represent Classification Functions Using Linear Decompositions (2021) (0)
On the Sensitivity of Boolean and Multiple-Valued Symmetric Functions (2022) (0)
A Hybrid Logic Simulator Using LUT Cascade Emulators (2007) (0)
Electronic Properties of Deep Level Defects in Thermally Annealed CZ Silicon (1986) (0)
Exact and Heuristic Minimization of the . . . (2005) (0)
Cascade-Based Synthesis (2011) (0)
Implementations ofReconfigurable LogicArrays on FPGAs (2007) (0)
A Fast Method to Evaluate Multiple - Output Logic Functions using BDDs (2002) (0)
Survey of Research Projects Conducted by Sasao’s Group (2004) (0)
A Fault Tolerant Look-Up Table Cascade Emulator (2006) (0)
A Fast Method for Exactly Optimum Linear Decomposition of Index Generation Functions (2022) (0)
Heuristic Optimization of Two-Level Networks (1999) (0)
Piecewise Arithmetic Expressions of Numeric Functions and Their Application to Design of Numeric Function Generators (2014) (0)
Hash-Based Synthesis (2011) (0)
How do earth tides affect astronomers (1978) (0)
On the Piropeirtie § of Multiple~ Valued Fmnctions That A:re Symmet:rk in Both Variable Values and Labels (2014) (0)
Functions with Small C-Measures (2011) (0)
Probe location checker for IC physical verification (2017) (0)
Definitions and Basic Properties (2011) (0)
A Design Algorithm for Sequential Circuit Synthesis using LUT Ring (2004) (0)
Programmable Hardware Implementation Based on Four Walsh Sequences (2007) (0)
Design Methods for Binary to Decimal Converters Using Arithmetic Decompositions (2007) (0)
PAPER Special Section on VLSI Design and CAD Algorithms Representations of Multiple-Output Functions Using Binary Decision Diagrams for Characteristic Functions (1999) (0)
An Update Method for a Low Power Cam Emulator Using an LUT Cascade Based on an EVMDD (k) (2016) (0)
A Heterogeneous Multi-valued Decision Diagram Machine for Encoded Characteristic Function for Non-zero Outputs (2014) (0)
A Method To Generate Rules From Examples (2022) (0)
Reeducation for Design Engineers in Fukuoka System LSI College (2012) (0)
Optimization of Sequential Networks (1999) (0)
Numeric Function Generators Using Decision Diagrams for Discrete Functions (2009) (0)
LUT Cascade Realization of Threshold Functions and Its Application to Implementation of Ternary Weight Neural Networks (2022) (0)
On a Minimization of Generalized Reed-Muller Expressions (1994) (0)
DAC2005 Incompletely Specified Benchmark Function Set (2005) (0)
Numeric Function Generators (2009) (0)
Linear Decompositions for Multi-Valued Input Classification Functions (2021) (0)
Complexity of networks realized by fiber optic logic elements (1990) (0)
On LUT Cascade Realizations of FIR Filters Using Arithmetic Decomposition (2005) (0)
Time-Division Multiplexing Realizations of Multiple-Terminal Multiple-Valued Decision Diagrams (1999) (0)
A set partition number system (2016) (0)
A software system for collecting and displaying informations on the computer system activities. (1987) (0)
Logic Functions and Their Representations (1999) (0)

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