Valeria Bertacco
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Academic and researcher in electrical engineering and computer science
Valeria Bertacco's AcademicInfluence.com Rankings
Valeria Bertaccoengineering Degrees
Engineering
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#8439
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Electrical Engineering
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Valeria Bertaccocomputer-science Degrees
Computer Science
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Engineering Computer Science
Why Is Valeria Bertacco Influential?
(Suggest an Edit or Addition)According to Wikipedia, Valeria Bertacco is a professor of Electrical Engineering and Computer Science as well as Vice Provost for Engaged Learning at the University of Michigan. She previously served as the Associate Dean for Academic Programs and Initiatives at the University of Michigan Rackham Graduate School.
Valeria Bertacco's Published Works
Number of citations in a given year to any of this author's works
Total number of citations to an author for the works they published in a given year. This highlights publication of the most important work(s) by the author
Published Works
- A highly resilient routing algorithm for fault-tolerant NoCs (2009) (249)
- Vicis: A reliable network for unreliable silicon (2009) (209)
- BulletProof: a defect-tolerant CMP switch architecture (2006) (207)
- Opportunities and challenges for better than worst-case design (2005) (163)
- Smart simulation using collaborative formal and simulation engines (2000) (141)
- Software-Based Online Detection of Hardware Defects Mechanisms, Architectural Support, and Evaluation (2007) (137)
- Ultra low-cost defect protection for microprocessor pipelines (2006) (135)
- The disjunctive decomposition of logic functions (1997) (127)
- Regaining lost cycles with HotCalls: A fast interface for SGX secure enclaves (2017) (119)
- Event-driven gate-level simulation with GP-GPUs (2009) (106)
- Fault-based attack of RSA authentication (2010) (104)
- ARIADNE: Agnostic Reconfiguration in a Disconnected Network Environment (2011) (101)
- A Reliable Routing Architecture and Algorithm for NoCs (2012) (93)
- Fixing Design Errors with Counterexamples and Resynthesis (2007) (87)
- Decision Diagrams and Pass Transistor Logic Synthesis (1997) (86)
- Power-aware NoCs through routing and topology reconfiguration (2014) (86)
- Automating post-silicon debugging and repair (2007) (80)
- Reliable Systems on Unreliable Fabrics (2008) (73)
- Simulation-based signal selection for state restoration in silicon debug (2011) (71)
- CrashTest: A fast high-fidelity FPGA-based resiliency analysis framework (2008) (69)
- At-Speed Distributed Functional Testing to Detect Logic and Delay Faults in NoCs (2014) (68)
- GCS: High-performance gate-level simulation with GPGPUs (2009) (67)
- A distributed and topology-agnostic approach for on-line NoC testing (2011) (66)
- StressTest: an automatic approach to test generation via activity monitors (2005) (60)
- Shielding against design flaws with field repairable control logic (2006) (55)
- Dacota: Post-silicon validation of the memory subsystem in multi-core designs (2009) (55)
- Comprehensive online defect diagnosis in on-chip networks (2012) (54)
- Reversi: Post-silicon validation system for modern microprocessors (2008) (53)
- Microprocessor Verification via Feedback-Adjusted Markov Models (2007) (52)
- Simulation-based bug trace minimization with BMC-based refinement (2005) (50)
- Node Mergers in the Presence of Don't Cares (2007) (48)
- Automatic error diagnosis and correction for RTL designs (2007) (48)
- Bridging pre-silicon verification and post-silicon validation (2010) (47)
- uDIREC: Unified diagnosis and reconfiguration for frugal bypass of NoC faults (2013) (45)
- Distance-Guided Hybrid Verification with GUIDO (2006) (42)
- Machine learning-based anomaly detection for post-silicon bug diagnosis (2013) (42)
- ReliNoC: A reliable network for priority-based on-chip communication (2011) (42)
- Formally enhanced runtime verification to ensure NoC functional correctness (2011) (41)
- A Flexible Software-Based Framework for Online Detection of Hardware Defects (2009) (40)
- Morpheus: A Vulnerability-Tolerant Secure Architecture Based on Ensembles of Moving Target Defenses with Churn (2019) (40)
- Post-silicon verification for cache coherence (2008) (38)
- Engineering Trust with Semantic Guardians (2007) (35)
- SAGA: SystemC acceleration on GPU architectures (2012) (31)
- CrashTest'ing SWAT: Accurate, gate-level evaluation of symptom-based resiliency solutions (2012) (29)
- Low-Cost Protection for SER Upsets and Silicon Defects (2007) (29)
- Brisk and limited-impact NoC routing reconfiguration (2014) (28)
- Reap what you sow: spare cells for post-silicon metal fix (2008) (28)
- Post-Silicon and Runtime Verification for Modern Processors (2010) (28)
- Gate-Level Simulation with GPU Computing (2011) (27)
- Deployment of better than worst-case design: solutions and needs (2005) (26)
- Scalable Hardware Verification with Symbolic Simulation (2010) (24)
- Viper: Virtual pipelines for enhanced reliability (2012) (24)
- Restoring Circuit Structure from SAT Instances (2004) (23)
- Post-silicon bug diagnosis with inconsistent executions (2011) (23)
- Heterogeneous Memory Subsystem for Natural Graph Analytics (2018) (22)
- DRAIN: Distributed Recovery Architecture for Inaccessible Nodes in multi-core chips (2011) (21)
- Microarchitectural power modeling techniques for deep sub-micron microprocessors (2004) (20)
- Random Stimulus Generation using Entropy and XOR Constraints (2008) (20)
- Using Field-Repairable Control Logic to Correct Design Errors in Microprocessors (2008) (20)
- Inferno: Streamlining Verification With Inferred Semantics (2009) (19)
- Post-placement rewiring and rebuffering by exhaustive search for functional symmetries (2005) (19)
- ForEVeR (2014) (18)
- Cycle-based symbolic simulation of gate-level synchronous circuits (1999) (18)
- Testudo: Heavyweight security analysis via statistical sampling (2008) (18)
- Veri cation Through the Principle of Least Astonishment (2006) (17)
- Functional post-silicon diagnosis and debug for networks-on-chip (2012) (17)
- MCjammer: Adaptive Verification for Multi-core Designs (2008) (17)
- Application-Aware diagnosis of runtime hardware faults (2010) (17)
- Human computing for EDA (2009) (17)
- Optimizing Nonmonotonic Interconnect Using Functional Simulation and Logic Restructuring (2008) (17)
- Caspar: Hardware patching for multicore processors (2009) (16)
- SystemC simulation on GP-GPUs: CUDA vs. OpenCL (2012) (16)
- Distance-Guided Hybrid Verification with GUIDO (2006) (15)
- Safe Delay Optimization for Physical Synthesis (2007) (15)
- Logic synthesis and circuit customization using extensive external don't-cares (2010) (15)
- Highly Fault-tolerant NoC Routing with Application-aware Congestion Management (2015) (14)
- Post-silicon platform for the functional diagnosis and debug of networks-on-chip (2014) (14)
- Functional correctness for CMP interconnects (2011) (14)
- High-radix on-chip networks with low-radix routers (2014) (13)
- Assessing SEU Vulnerability via Circuit-Level Timing Analysis (2005) (13)
- Boolean function representation based on disjoint-support decompositions (1996) (13)
- InVerS: An Incremental Verification System with Circuit Similarity Metrics and Error Visualization (2007) (13)
- ForEVeR: A complementary formal and runtime verification approach to correct NoC functionality (2014) (13)
- Bridging pre- and post-silicon debugging with BiPeD (2012) (12)
- Checking architectural outputs instruction-by-instruction on acceleration platforms (2012) (12)
- Advances and Insights into Parallel SAT Solving (11)
- Highly scalable distributed dataflow analysis (2011) (11)
- Post-Silicon Validation of Multiprocessor Memory Consistency (2015) (11)
- BugMD: Automatic Mismatch Diagnosis for Bug triaging (2016) (11)
- Efficient state representation for symbolic simulation (2002) (11)
- On the use of GP-GPUs for accelerating compute-intensive EDA applications (2013) (10)
- Architecting a reliable CMP switch architecture (2007) (10)
- Postplacement rewiring by exhaustive search for functional symmetries (2007) (9)
- STACCATO: disjoint support decompositions from BDDs through symbolic kernels (2005) (9)
- Circuit-aware architectural simulation (2004) (9)
- DREDGE: Dynamic Repartitioning during Dynamic Graph Execution (2019) (8)
- Viper (2012) (8)
- Approximating checkers for simulation acceleration (2012) (7)
- SWAN: Mitigating Hardware Trojans with Design Ambiguity (2018) (7)
- MTraceCheck: Validating non-deterministic behavior of memory consistency models in post-silicon validation (2017) (7)
- Collaborative accelerators for in-memory MapReduce on scale-up machines (2019) (6)
- Resource Conscious Diagnosis and Reconfiguration for NoC Permanent Faults (2016) (6)
- Centaur: Hybrid Processing in On/Off-chip Memory Architecture for Graph Analytics (2020) (6)
- Collaborative Accelerators for Streamlining MapReduce on Scale-up Machines With Incremental Data Aggregation (2020) (6)
- Functional Design Errors in Digital Circuits - Diagnosis, Correction and Repair (2008) (5)
- Cardio: Adaptive CMPs for reliability through dynamic introspective operation (2011) (5)
- Boolean function representation using parallel-access diagrams (1996) (5)
- EQUIPE: Parallel equivalence checking with GP-GPUs (2010) (5)
- Chico: An On-chip Hardware Checker for Pipeline Control Logic (2007) (5)
- VOLTaiRE : Low-cost Fault Detection Solutions for VLIW Microprocessors (5)
- Achieving scalable hardware verification with symbolic simulation (2003) (5)
- SafeResynth: A new technique for physical synthesis (2008) (5)
- Low-latency SAT Solving on Multicore Processors with Priority Scheduling and XOR Partitioning (5)
- Morpheus II: A RISC-V Security Extension for Protecting Vulnerable Software and Hardware (2021) (4)
- Cardio: CMP Adaptation for Reliability Through Dynamic Introspective Operation (2014) (4)
- Compute-Capable Block RAMs for Efficient Deep Learning Acceleration on FPGAs (2021) (4)
- ItHELPS: Iterative high-accuracy error localization in post-silicon (2015) (4)
- Humans for EDA and EDA for humans (2012) (4)
- Energy efficient object detection on the mobile GP-GPU (2017) (4)
- Symbolic assertion mining for security validation (2018) (4)
- High performance gate-level simulation with GP-GPU computing (2011) (4)
- Probabilistic bug-masking analysis for post-silicon tests in microprocessor verification (2016) (4)
- SiPterposer: A Fault-Tolerant Substrate for Flexible System-in-Package Design (2019) (4)
- Post-silicon debugging for multi-core designs (2010) (4)
- DiAMOND:Distributed alteration of messages for on-chip network debug (2014) (4)
- GraphVine: Exploiting Multicast for Scalable Graph Analytics (2020) (4)
- DOVE: pinpointing firmware security vulnerabilities via symbolic control flow assertion mining (work-in-progress) (2017) (3)
- SoCGuard: A runtime verification solution for the functional correctness of SoCs (2010) (3)
- Keeping Physical Synthesis Safe and Sound (3)
- MessageFusion: On-path Message Coalescing for Energy Efficient and Scalable Graph Analytics (2019) (3)
- Correct runtime operation for NoCs through adaptive-region protection (2016) (3)
- 3DFAR: A three-dimensional fabric for reliable multi-core processors (2017) (3)
- Boolean Operations on Decomposed Functions (3)
- Schnauzer: scalable profiling for likely security bug sites (2013) (3)
- Formally Enhanced Verification at Runtime to Ensure NoC Functional Correctness (2011) (3)
- Toggle : A Coverage-guided Random Stimulus Generator (2007) (3)
- Student perceptions of their abilities and learning environment in large introductory computer programming courses (2017) (3)
- Morpheus (2019) (3)
- Low-Overhead Microarchitectural Patching for Multicore Memory Subsystems (2018) (3)
- Incremental Verification with Error Detection, Diagnosis, and Visualization (2009) (3)
- Work-in-Progress: DOVE: Pinpointing firmware security vulnerabilities via symbolic control flow assertion mining (2017) (3)
- Cobra: A comprehensive bundle-based reliable architecture (2013) (3)
- Customizing IP cores for system-on-chip designs using extensive external don't-cares (2009) (3)
- Bug Trace Minimization (2009) (3)
- High Radix On-Chip Networks at Incremental Reconfiguration Cost (2014) (2)
- Activity-based refinement for abstraction-guided simulation (2009) (2)
- SNIFFER: A high-accuracy malware detector for enterprise-based systems (2017) (2)
- ArChiVED: Architectural checking via event digests for high performance validation (2014) (2)
- Neksus: An Interconnect for Heterogeneous System-In-Package Architectures (2020) (2)
- PowerRanger: Assessing circuit vulnerability to power attacks using SAT-based static analysis (2009) (2)
- Architectural Trace-Based Functional Coverage for Multiprocessor Verification (2012) (2)
- Cycle-based Symbolic Simulation of Synchronous Circuits (1999) (2)
- Depth-driven verification of simultaneous interfaces (2006) (2)
- Microprocessor Verification via (2007) (2)
- Hardware and Software: Verification and Testing (2013) (1)
- Hybrid checking for microarchitectural validation of microprocessor designs on acceleration platforms (2013) (1)
- Optimizing Vertex Pressure Dynamic Graph Partitioning in Many-Core Systems (2021) (1)
- Fast Simulation and Equivalence Checking Using OAGear (1)
- Formal verification for real-world designs (2006) (1)
- Chopin: Composing Cost-Effective Custom Chips with Algorithmic Chiplets (2021) (1)
- Finding complex disjunctive decompositions of logic functions (2002) (1)
- Vulnerability-Tolerant Secure Architectures (2018) (1)
- Post-Silicon Verification of Multi-Core Processors (2011) (1)
- Microarchitectural Power Modeling Techniques for Deep SubMicron (2002) (1)
- ChipAdvisor: A Machine Learning Approach for Mapping Applications to Heterogeneous Systems (2021) (1)
- GUIDO : Hybrid Verification by Distance-Guided Simulation (1)
- ReDEEM: A heterogeneous distributed microarchitecture for energy-efficient reliability (2015) (1)
- EQUIPE : Parallel Equivalence Checking with GPU ’ s (2010) (1)
- Panel: When will the cost of dependability end innovation in computer design? (2015) (1)
- Electronic design automation for social networks (2010) (1)
- Current Landscape in Design and Verification (2009) (1)
- Low maintenance verification (2006) (0)
- Methodologies for Spare-Cell Insertion (2009) (0)
- Verification of a Modern Processor (2011) (0)
- Incremental Verification for Physical Synthesis (2009) (0)
- Debugging strategies for mere mortals (2009) (0)
- PriMax: maximizing DSL application performance with selective primitive acceleration (2022) (0)
- Session details: Wild and crazy ideas (2011) (0)
- MyML: User-Driven Machine Learning (2021) (0)
- ArChIVED : High Performance Validation of Microprocessors Using Event Digests (2013) (0)
- OPTIMIZING VIDEO SCALERS USING REAL-TIME VERIFICATION TECHNIQUES (2009) (0)
- Symmetry-Based Rewiring (2009) (0)
- Patching Design Flaws in Multicore Memory Subsystems (2018) (0)
- FPGA Synthesis and CAD for Reconfigurable Systems (2009) (0)
- 3 DFAR : A Three-Dimensional Fabric for Reliable Multi-Core Processors (2017) (0)
- Author Index (2013) (0)
- Circuit Design and Verification Methodologies (2009) (0)
- Functional Error Diagnosis and Correction (2009) (0)
- Thwarting Control Plane Attacks with Displaced and Dilated Address Spaces (2020) (0)
- Post-Silicon Debugging and Layout Repair (2009) (0)
- Formal verification for real-world designs: today's technologies [Tutorial] (2004) (0)
- XPV : Cross Phase Verification (2011) (0)
- Simulation-Based Signal Selection (2018) (0)
- Feasibility of Optical Interconnection Networks Theory and Case Study (0)
- LinkMiser : Resource Conscious Routing and Reconfiguration in Faulty On-Chip Networks (2012) (0)
- DyGraph (2022) (0)
- Test Generation and Lightweight Checking for Multi-core Memory Consistency (2018) (0)
- Seesaw: End-to-end Dynamic Sensing for IoT using Machine Learning (2020) (0)
- GreenScale: Carbon-Aware Systems for Edge Computing (2023) (0)
- The Verification Universe (2011) (0)
- Morpheus II: A RISC-V Security Extension for Protecting Vulnerable Software and Hardware (2021) (0)
- PriMax (2022) (0)
- DyGraph: a dynamic graph generator and benchmark suite (2022) (0)
- 09461 Abstracts Collection - Algorithms and Applications for Next Generation SAT Solvers (2009) (0)
- Session details: Formal techniques to enhance the verification flow (2007) (0)
- Verification Failures: What to Do When Things Go Wrong (2010) (0)
- Synthesis with External Don ’ t-Cares Using Shannon Entropy and Craig Interpolation (2008) (0)
- Message from the ISCA 2020 Program Chair (2020) (0)
- SWAN (2018) (0)
- Ensuring Correctness in Future Microprocessors (2011) (0)
- Consistency Verification using Data Coloring (2011) (0)
- MR . NITRO : Distributed Accelerators for MapReduce on CMPs (2016) (0)
- International (1964) (0)
- Signature-Based Resynthesis Techniques (2009) (0)
- Session details: High-level models for validation (2008) (0)
- MCjammer : An Adaptive Verification Tool for Multi-core and Multi-processor Designs (2007) (0)
- M icroarc h itect u ral Power MO ng Techniques for Deep Su b-Micron Microprocessors* (2004) (0)
- AHighlyResilientRoutingAlgorithmforFaultTolerantNoC s (2009) (0)
- Runtime Verification in Multi-Cores (2011) (0)
- Hardware-friendly User-specific Machine Learning for Edge Devices (2022) (0)
- NoCVision: A Network-on-Chip Dynamic Visualization Solution (2015) (0)
- Bypassing Multicore Memory Bugs With Coarse-Grained Reconfigurable Logic (2022) (0)
- Session details: Special session: wild and crazy ideas (2008) (0)
- Runtime Verification with Patching and Hardware Checkers (2011) (0)
- Debug Data Collection for Functional Validation of Control-Flow in NoCs (2014) (0)
- Panel: Software practices for verification/testbench management (2008) (0)
- Post-Silicon Validation of Processor Cores (2011) (0)
- Design in the Late-and Post-Silicon Eras (2008) (0)
- Fast Verification of Retiming (0)
- AGARSoC: Automated test and coverage-model generation for verification of accelerator-rich SoCs (2017) (0)
- Counterexample-Guided Error-Repair Framework (2009) (0)
- Hardware Patching with Field-Repairable Control Logic (2011) (0)
- DREDGE (2019) (0)
- Finding Bugs and Repairing Circuits (2009) (0)
- A Defense-Inspired Benchmark Suite (2021) (0)
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What Schools Are Affiliated With Valeria Bertacco?
Valeria Bertacco is affiliated with the following schools:
