Vishwani Agrawal

Q: What Schools Are Affiliated With Vishwani Agrawal

Vishwani Agrawal is affiliated with the following schools: Auburn University, Indian Institute of Science, University of South Florida, Stanford University, University of California, Santa Cruz

Vishwani Agrawal's AcademicInfluence.com Rankings

Vishwani Agrawal

Engineering

#3086

World Rank

#4110

Historical Rank

Electrical Engineering

#663

World Rank

#725

Historical Rank

engineering Degrees

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Engineering

Vishwani Agrawal's Degrees

PhD Electrical Engineering Stanford University
Masters Electrical Engineering Stanford University

Why Is Vishwani Agrawal Influential?

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According to Wikipedia, Vishwani D. Agrawal is the James J. Danaher Professor of Electrical and Computer Engineering at Auburn University. He has over four decades of industry and university experience, including working at Bell Labs, Murray Hill, NJ, Rutgers University, TRW and IIT, Delhi. He is well known as a cofounder and long-term mentor of the International Conference on VLSI Design held annually in India since 1985.

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Vishwani Agrawal's Published Works

Number of citations in a given year to any of this author's works

Total number of citations to an author for the works they published in a given year. This highlights publication of the most important work(s) by the author

Published Works

Essentials of electronic testing for digital, memory, and mixed-signal VLSI circuits [Book Review] (2000) (1540)
A Partial Scan Method for Sequential Circuits with Feedback (1990) (327)
Scheduling tests for VLSI systems under power constraints (1997) (304)
A Tutorial on Built-in Self-Test. I. Principles (1993) (261)
A Tutorial on Built-In Self-Test, Part 2: Applications (1993) (193)
Design of a dichroic Cassegrain subreflector (1979) (180)
A transitive closure algorithm for test generation (1993) (180)
Chip Layout Optimization Using Critical Path Weighting (1984) (177)
Single Event Upset: An Embedded Tutorial (2008) (156)
Statistical Fault Analysis (1985) (147)
Test Generation for MOS Circuits Using D-Algorithm (1983) (138)
An exact algorithm for selecting partial scan flip-flops (1994) (138)
Designing circuits with partial scan (1988) (118)
Segment delay faults: a new fault model (1996) (115)
Fault coverage requirement in production testing of LSI circuits (1982) (109)
Delay fault models and test generation for random logic sequential circuits (1992) (102)
STAFAN: An Alternative to Fault Simulation (1984) (102)
A directed search method for test generation using a concurrent simulator (1989) (97)
An economical scan design for sequential logic test generation (1989) (95)
A Statistical Theory of Digital Circuit Testability (1990) (94)
Power constraint scheduling of tests (1994) (93)
Combinational ATPG theorems for identifying untestable faults in sequential circuits (1993) (90)
An Information Theoretic Approach to Digital Fault Testing (1981) (90)
Classification and Test Generation for Path-Delay Faults Using Single Struck-at Fault Tests (1995) (89)
CONTEST: a concurrent test generator for sequential circuits (1988) (86)
Probabilistic Analysis of Random Test Generation Method for Irredundant Combinational Logic Networks (1975) (82)
Testability Measures : What Do They Tell Us ? (1982) (77)
An entropy measure for the complexity of multi-output Boolean functions (1990) (70)
A Gate Level Model for CMOS Combinational Logic Circuits with Application to Fault Detection (1984) (67)
Test Generation for Path Delay Faults Using Binary Decision Diagrams (1995) (67)
A Complete Solution to The Partial Scan Problem (1987) (67)
Characterizing the LSI Yield Equation from Wafer Test Data (1984) (66)
Fast identification of untestable delay faults using implications (1997) (64)
Modeling and Test Generation Algorithms for MOS Circuits (1985) (62)
Mutual coupling in phased arrays of randomly spaced antennas (1972) (60)
A new model for computation of probabilistic testability in combinational circuits (1989) (60)
Built-in self-test for digital integrated circuits (1994) (59)
Pascant: a partial scan and test generation system (1991) (56)
Exclusive test and its applications to fault diagnosis (2003) (55)
Synchronous Path Analysis in MOS Circuit Simulator (1982) (55)
Efficient spectral techniques for sequential ATPG (2001) (54)
A new algorithm for global fault collapsing into equivalence and dominance sets (2002) (54)
High-performance circuit testing with slow-speed testers (1995) (51)
When to Use Random Testing (1978) (51)
Variable Input Delay CMOS Logic for Low Power Design (2005) (50)
A diagnostic test generation system (2010) (50)
AN EXACT ANALYSIS FOR EFFICIENT COMPUTATION OF RANDOM-PATTERN TESTABILITY IN COMBINATIONAL CIRCUITS (1986) (50)
Toward massively parallel automatic test generation (1990) (49)
Unified Methods for VLSI Simulation and Test Generation (1989) (49)
An experimental study on reject ratio prediction for VLSI circuits: Kokomo revisited (1990) (49)
Delay fault test generation for scan/hold circuits using Boolean expressions (1992) (45)
Fault collapsing via functional dominance (2003) (45)
Generation of compact delay tests by multiple path activation (1993) (45)
Low-power design by hazard filtering (1997) (43)
Generating tests for delay faults in nonscan circuits (1993) (42)
Path delay fault simulation of sequential circuits (1993) (42)
Fault simulation in a pipelined multiprocessor system (1989) (41)
Performance Analysis of Synchronized Iterative Algorithms on Multiprocessor Systems (1992) (41)
Diagnostic and detection fault collapsing for multiple output circuits (2005) (40)
Validation vector grade (VVG): a new coverage metric for validation and test (1999) (40)
Initializability Consideration in Sequential Machine Synthesis (1992) (40)
Neural Models and Algorithms for Digital Testing (1991) (40)
A random access scans architecture to reduce hardware overhead (2005) (40)
An Automatic Test Generation System for Illiac IV Logic Boards (1972) (39)
Digital circuit design for minimum transient energy and a linear programming method (1999) (38)
Tutorial: Delay Fault Models and Coverage (1998) (38)
On test coverage of path delay faults (1996) (37)
Multiple faults: modeling, simulation and test (2002) (36)
An efficient test data reduction technique through dynamic pattern mixing across multiple fault models (2011) (36)
The path-status graph with application to delay fault simulation (1998) (35)
Distribution of sidelobe level in random arrays (1969) (34)
Delay fault models and coverage (1998) (33)
STATE ASSIGNMENT FOR INITIALIZABLE SYNTHESIS (1989) (33)
Minimum dynamic power CMOS circuit design by a reduced constraint set linear program (2003) (32)
Neural net and Boolean satisfiability models of logic circuits (1990) (32)
Design of sequential machines for efficient test generation (1989) (32)
Polynomial coefficient based DC testing of non-linear analog circuits (2009) (31)
Finite state machine synthesis with fault tolerant test function (1992) (30)
A transitive closure based algorithm for test generation (1991) (30)
Automatic test generation using neural networks (1988) (30)
Fault sampling revisited (1990) (30)
A New Method for Generating Tests for Delay Faults in Non-Scan Circuits (1992) (29)
Register-transfer level fault modeling and test evaluation techniques for VLSI circuits (2000) (29)
Sequential Circuit Test Generation on a Distributed System (1993) (28)
A Two Phase Approach for Minimal Diagnostic Test Set Generation (2009) (28)
A tutorial on the emerging nanotechnology devices (2004) (27)
Securing IEEE 1687-2014 Standard Instrumentation Access by LFSR Key (2015) (27)
On Minimization of Peak Power for Scan Circuit during Test (2009) (27)
Finite state machine synthesis with embedded test function (1990) (27)
Minimum energy CMOS design with dual subthreshold supply and multiple logic-level gates (2011) (26)
Grating-lobe suppression in phased arrays by subarray rotation (1978) (26)
Soft error rate determination for nanoscale sequential logic (2010) (26)
On Monte Carlo Testing of Logic Tree Networks (1976) (25)
LSI Product Quality and Fault Coverage (1981) (25)
Reducing the complexity of defect level modeling using the clustering effect (2000) (25)
Design for Testability for Path Delay Faults in Sequential Circuits (1993) (25)
Test function embedding algorithms with application to interconnected finite state machines (1993) (25)
An exact non-enumerative fault simulator for path-delay faults (1996) (25)
Dynamic scan clock control for test time reduction maintaining peak power limit (2011) (24)
Novel spectral methods for built-in self-test in a system-on-a-chip environment (2001) (24)
CMOS Leakage and Glitch Minimization for Power-Performance Tradeoff (2006) (24)
Concurrent test generation and design for testability (1989) (24)
Tutorial test generation for VLSI chips (1988) (23)
A Mixed-Mode Simulator (1980) (23)
On the Probability of Fault Occurrence (1989) (23)
A Reduced Complexity Algorithm for Minimizing N-Detect Tests (2007) (22)
Test generation by fault sampling (1988) (22)
Concurrent and comparative discrete event simulation (1993) (22)
On random pattern generation with the selfish gene algorithm for testing digital sequential circuits (2004) (22)
On variable clock methods for path delay testing of sequential circuits (1997) (22)
Multi-tone Testing of Linear and Nonlinear Analog Circuits Using Polynomial Coefficients (2009) (22)
Optimal power-constrained SoC test schedules with customizable clock rates (2012) (21)
Ultra Low Energy CMOS Logic Using Below-Threshold Dual-Voltage Supply (2011) (21)
An Efficient Path Delay Fault Coverage Estimator (1994) (21)
Test and Diagnosis of Analog Circuits Using Moment Generating Functions (2011) (21)
IEEE Transactions on Very Large Scale Integration (VLSI) Systems (2018) (21)
Soft Error Rate Determination for Nanometer CMOS VLSI Logic (2008) (20)
Logic systems for path delay test generation (1993) (20)
Energy source lifetime optimization for a digital system through power management (2011) (20)
Spectral RTL Test Generation for Gate-Level Stuck-at Faults (2006) (20)
State assignment for initializable synthesis (gate level analysis) (1989) (20)
Parametric Fault Testing of Non-Linear Analog Circuits Based on Polynomial and V-Transform Coefficients (2012) (20)
A test evaluation technique for VLSI circuits using register-transfer level fault modeling (2003) (20)
Delay fault simulation with bounded gate delay mode (2007) (20)
Modeling and test generation for combinational hardware Trojans (2018) (19)
Reduced complexity test generation algorithms for transition fault diagnosis (2011) (19)
CMOS circuit design for minimum dynamic power and highest speed (2004) (18)
A partition and resynthesis approach to testable design of large circuits (1995) (18)
An architecture for synthesis of testable finite state machines (1990) (18)
Cutting chip-testing costs (1985) (18)
Improving accuracy in path delay fault coverage estimation (1996) (18)
True Minimum Energy Design Using Dual Below-Threshold Supply Voltages (2011) (18)
A novel clocking technique for VLSI circuit testability (1984) (17)
Clock partitioning for testability (1993) (17)
A sequential circuit test generation using threshold-value simulation (1988) (17)
FACTS: fault coverage estimation by test vector sampling (1994) (17)
Built-in Self-Calibration of On-chip DAC and ADC (2008) (17)
Effective path selection for delay fault testing of sequential circuits (1997) (17)
A Test Time Theorem and its Applications (2013) (17)
Externally Tested Scan Circuit with Built-In Activity Monitor and Adaptive Test Clock (2012) (17)
Automatic test generation using quadratic 0-1 programming (1990) (17)
A synthesis approach to design for testability (1993) (16)
A Path Delay Fault Simulator for Sequential Circuits (1993) (16)
Statistical Leakage and Timing Optimization for Submicron Process Variation (2007) (16)
Multiple fault detection in two-level multi-output circuits (1992) (16)
A rated-clock test method for path delay faults (1998) (16)
Improving a nonenumerative method to estimate path delay fault coverage (1997) (16)
Energy minimization and design for testability (1994) (16)
Combinational test generation for various classes of acyclic sequential circuits (2001) (16)
Redundancy identification using transitive closure (1996) (15)
Optimum Test Schedule for SoC with Specified Clock Frequencies and Supply Voltages (2013) (15)
Enhanced dual-transition probabilistic power estimation with selective supergate analysis (2005) (15)
Multiple Output Minimization (1985) (15)
Statistical methods for delay fault coverage analysis (1995) (15)
Power Dissipation During Testing: Should We Worry About it? (1997) (15)
Power-aware SoC test optimization through dynamic voltage and frequency scaling (2013) (15)
Mixed-signal test (1998) (15)
Path delay testing: variable-clock versus rated-clock (1998) (15)
SPARTAN: a spectral and information theoretic approach to partial-scan (2007) (15)
An efficient automatic test generation system for path delay faults in combinational circuits (1995) (15)
Energy models for delay testing (1995) (15)
Redundancy removal and test generation for circuits with non-Boolean primitives (1995) (14)
Leakage and Dynamic Glitch Power Minimization Using Integer Linear Programming for Vth Assignment and Path Balancing (2005) (14)
Spectral RTL Test Generation for Microprocessors (2007) (14)
Finite state machine synthesis with embedded test function (1990) (14)
An algorithm for diagnostic fault simulation (2010) (14)
Polynomial time solvable fault detection problems (1990) (14)
A Tutorial on Battery Simulation - Matching Power Source to Electronic System (2010) (14)
Analog macromodeling of capacitive coupling faults in digital circuit interconnects (2002) (14)
Performance estimation in a massively parallel system (1990) (14)
High-Level Test Generation for Gate-Level Fault Coverage (2006) (14)
Soft Error Rates with Inertial and Logical Masking (2009) (14)
A parallel-vector concurrent-fault simulator and generation of single-input-change tests for path-delay faults (1998) (13)
Deriving Logic Systems for Path Delay Test Generation (1998) (13)
Reducing Test Time of Power Constrained Test by Optimal Selection of Supply Voltage (2013) (13)
Improving path delay testability of sequential circuits (2000) (13)
Dual-transition glitch filtering in probabilistic waveform power estimation (2005) (13)
Dual voltage design for minimum energy using gate slack (2011) (13)
INDEPENDENCE FAULT COLLAPSING (2005) (13)
Sequential logic path delay test generation by symbolic analysis (1995) (13)
Fault coverage estimation by test vector sampling (1995) (12)
SIGMA: A simulator for segment delay faults (1996) (12)
Parametric Fault Diagnosis of Nonlinear Analog Circuits Using Polynomial Coefficients (2010) (12)
The optimistic update theorem for path delay testing in sequential circuits (1993) (12)
Transistor Sizing of Logic Gates to Maximize Input Delay Variability (2006) (12)
Applying Neural Networks to Delay Fault Testing: Test Point Insertion and Random Circuit Training (2019) (12)
Minimum dynamic power cmos design with variable input delay logic (2004) (12)
GLITCH-FREE DESIGN OF LOW POWER ASICS USING CUSTOMIZED RESISTIVE FEEDTHROUGH CELLS (2005) (12)
Improved Random Pattern Delay Fault Coverage Using Inversion Test Points (2019) (12)
A non-enumerative path delay fault simulator for sequential circuits (1998) (12)
Diagnostic Tests for Pre-bond TSV Defects (2015) (12)
Algorithms for Estimating Number of Glitches and Dynamic Power in CMOS Circuits with Delay Variations (2009) (11)
Delay Test Quality Evaluation Using Bounded Gate Delays (2007) (11)
Functional Test Generation for Sequential Circuits (1992) (11)
Mutually disjoint signals and probability calculation in digital circuits (1998) (11)
Synthesis of testable finite state machines (1990) (11)
Characteristic polynomial method for verification and test of combinational circuits (1996) (11)
Finding best voltage and frequency to shorten power-constrained test time (2013) (11)
N-Model Tests for VLSI Circuits (2008) (11)
Input-specific Dynamic Power Optimization for VLSI Circuits (2006) (11)
Logic simulation and parallel processing (1990) (11)
An optimal probing method of pre-bond TSV fault identification in 3D stacked ICs (2014) (10)
ATE test time reduction using asynchronous clock period (2013) (10)
A testability metric for path delay faults and its application (2000) (10)
Gutting chip-testing costs: Designing VLSI circuits for testability is the most efficient way to reduce the relative costs of assuring high chip reliability (1985) (10)
New graphical I/sub DDQ/ signatures reduce defect level and yield loss (2003) (10)
Editorial—Special issue on partial scan design (1995) (10)
A test function architecture for interconnected finite state machines (1994) (10)
Dynamic scan clock control in BIST circuits (2011) (10)
Testing linear and non-linear analog circuits using moment generating functions (2011) (10)
Editorial (2019) (10)
Diagnostic Test Set Minimization and Full-Response Fault Dictionary (2012) (10)
Tailoring Tests for Functional Binning of Integrated Circuits (2012) (10)
A test generator for segment delay faults (1999) (10)
Adder and comparator synthesis with exclusive-OR transform of inputs (1997) (10)
Accurate computation of field reject ratio based on fault latency (1993) (10)
Special Session – Machine Learning in Test: A Survey of Analog, Digital, Memory, and RF Integrated Circuits (2021) (10)
Parallel concurrent path-delay fault simulation using single-input change patterns (1996) (10)
A new transitive closure algorithm with application to redundancy identification (2002) (9)
Non-linear analog circuit test and diagnosis under process variation using V-Transform coefficients (2011) (9)
A Simulation-Based Method for Generating Tests for Sequential Circuits (1990) (9)
Output Hazard-Free Transition Delay Fault Test Generation (2009) (9)
False-Path Removal Using Delay Fault Simulation (1998) (9)
Machine Intelligence for Efficient Test Pattern Generation (2020) (9)
Improving circuit testability by clock control (1996) (9)
Concurrent Test Generation (2005) (9)
A fault-independent transitive closure algorithm for redundancy identification (2003) (9)
Defect Level and Fault Coverage in Coefficient Based Analog Circuit Testing (2012) (8)
Flags and algebra for sequential circuit VNR path delay fault test generation (1997) (8)
Combinational test generation for acyclic sequential circuits using a balanced ATPG model (2001) (8)
A tale of two designs: the cheapest and the most economic (1994) (8)
Fault Nodes in Implication Graph for Equivalence/Dominance Collapsing, and Identifying Untestable and Independent Faults (2008) (8)
A Novel Random Access Scan Flip-Flop Design (2005) (8)
Design of Variable Input Delay Gates for Low Dynamic Power Circuits (2005) (8)
Algorithms for switch level delay fault simulation (1997) (8)
A New Test Vector Search Algorithm for a Single Stuck-at Fault Using Probabilistic Correlation (2014) (8)
Net diagnosis using stuck-at and transition fault models (2012) (8)
Finite state machine testing based on growth and disappearance faults (1992) (8)
Yield analysis of a novel wafer manipulation method in 3D stacking (2013) (8)
Impact of process variations on computers used for image processing (2012) (8)
Quest for a quantum search algorithm for testing stuck-at faults in digital circuits (2015) (8)
Editorial (2019) (8)
Training Neural Network for Machine Intelligence in Automatic Test Pattern Generator (2021) (8)
Architectural power management for high leakage technologies (2011) (8)
Test function specification in synthesis (1990) (8)
Steering Committee Chair (1999) (7)
Functional test generation for synchronous sequential circuits (1996) (7)
Compaction-based test generation using state and fault information (2000) (7)
Total Power Minimization in Glitch-Free CMOS Circuits Considering Process Variation (2008) (7)
Combinational automatic test pattern generation for acyclic sequential circuits (2005) (7)
An adaptive distributed algorithm for sequential circuit test generation (1995) (7)
DynaTAPP: dynamic timing analysis with partial path activation in sequential circuits (1992) (7)
Managing performance and efficiency of a processor (2013) (7)
Using Hierarchy in Design Automation : The Fault Collapsing Problem (2007) (7)
Power Problems in VLSI Circuit Testing (2012) (7)
Soft error considerations for computer web servers (2010) (7)
Forecasting reject rate of tested LSI chips (1981) (7)
An optimized diagnostic procedure for pre-bond TSV defects (2014) (7)
Application of signal and noise theory to digital VLSI testing (2010) (6)
Comments on "An Approach to Highly Integrated Computer-Maintained Cellular Arrays" (1979) (6)
ESTIMATING THE QUALITY OF MANUFACTURED DIGITAL SEQUENTIAL CIRCUITS (1991) (6)
Synthesis of self-testing finite state machines from high-level specification (1996) (6)
Designing variation-tolerance in mixed-signal components of a system-on-chip (2009) (6)
BIST/TEST-DECOMPRESSOR DESIGN USING COMBINATIONAL TEST SPECTRUM (2009) (6)
The Comparative and Concurrent Simulation of discrete-event experiments (1992) (6)
Special Session: Delay Fault Testing - Present and Future (2019) (6)
On delay-untestable paths and stuck-fault redundancy (1998) (6)
Delay fault testability evaluation through timing simulation (1993) (6)
Test pattern generation for sequential circuits on a network of workstations (1993) (6)
Using Contrapositives to Enhance the Implication Graphs of Logic Circuits (2004) (5)
V-Transform: An Enhanced Polynomial Coefficient Based DC Test for Non-Linear Analog Circuits (2009) (5)
Applications of Mixed-Signal Technology in Digital Testing (2016) (5)
A method for removing blindness in phased arrays (1968) (5)
A Review of Carbon Nanotube Field Effect Transistors (2003) (5)
Test Generation for Highly Sequential Scan-Testable Circuits Through Logic Transformation (1981) (5)
An asynchronous algorithm for sequential circuit test generation on a network of workstations (1995) (5)
Variable Input Delay CMOS Logic Design for Low Dynamic Power Circuits (2005) (5)
Adopting multi-valued logic for reduced pin-count testing (2015) (5)
Upper bounding fault coverage by structural analysis and signal monitoring (2006) (5)
Multivalued Logic for Reduced Pin Count and Multi-site SoC Testing (2015) (5)
Quadratic 0-1 Programming (1991) (5)
Two-Pattern ∆IDDQ Test for Recycled IC Detection (2019) (5)
Special Session: Survey of Test Point Insertion for Logic Built-in Self-test (2020) (5)
Using contrapositive law in an implication graph (2005) (5)
Graphical $I_{\rm DDQ}$ Signatures Reduce Defect Level and Yield Loss (2007) (5)
A Novel Wafer Manipulation Method for Yield Improvement and Cost Reduction of 3D Wafer-on-Wafer Stacked ICs (2014) (5)
Database Search and ATPG -- Interdisciplinary Domains and Algorithms (2016) (5)
Transition Delay Fault Testing of Microprocessors by Spectral Method (2007) (5)
Robust testing for stuck-at faults (1995) (5)
A DSP-based ramp test for on-chip high-resolution ADC (2011) (5)
Numerical computation of characteristic polynomials of Boolean functions and its applications (1998) (5)
Sequential Circuit BIST Synthesis Using Spectrum and Noise from ATPG Patterns (2008) (5)
Chip layout optimization using critical path weighting (1984) (4)
A new classification of path-delay fault testability in terms of stuck-at faults (2004) (4)
An improved deductive fault simulator (1994) (4)
Improved Pseudo-Random Fault Coverage Through Inversions: a Study on Test Point Architectures (2020) (4)
Weighted Random and Transition Density Patterns For Scan-BIST ∗ (2012) (4)
Test-Time Reduction in ATE Using Asynchronous Clocking (2012) (4)
Design of mixed-signal systems for testability (1998) (4)
Testing With Reduced ATE Channels (2014) (4)
Wafer Cut and Rotation for Compound Yield Improvement in 3 D Wafer-on-Wafer Stacking (2013) (4)
High sensitivity test signatures for unconventional analog circuit test paradigms (2013) (4)
Retiming scan circuit to eliminate timing penalty (2012) (4)
Testing for faults, looking for defects (2011) (4)
Methods for synthesizing testable sequential circuits (1991) (4)
A complete characterization of path delay faults through stuck-at faults (1999) (4)
A high performance helical element for multiple access array on TDRSS spacecraft (1979) (4)
Threshold-Value Simulation and Test Generation (1988) (4)
Dual-threshold design of sub-threshold circuits (2013) (4)
Unsupervised Learning in Test Generation for Digital Integrated Circuits (2021) (4)
Probabilistic Soft Error Rate Estimation from Statistical SEU Parameters (2008) (4)
Scanning transients in phased-array antennas (1974) (4)
Three-Stage Optimization of Pre-Bond Diagnosis of TSV Defects (2017) (4)
Estimating Operational Age of an Integrated Circuit (2021) (3)
Failures Guide Probabilistic Search for a Hard-to-Find Test (2016) (3)
On Minimization of Peak Power during SoC Test (2009) (3)
Choice of tests for logic verification and equivalence checking and the use of fault simulation (2000) (3)
Analysis of frequency selective surfaces printed on dielectric sheet (1977) (3)
Power-Aware Optimization of SoC Test Schedules Using Voltage and Frequency Scaling (2017) (3)
Functional test generation for path delay faults (1995) (3)
Energy-Efficient Dual-Voltage Design Using Topological Constraints (2013) (3)
Statistical path delay fault coverage estimation for synchronous sequential circuits (1996) (3)
Frequency-spread associated with fast electronic scanning (1974) (3)
Experimental and theoretical design of dichroic surface for a spacecraft antenna (1976) (3)
Will Testability Analysis Replace Fault Simulation ? (1984) (3)
Use of Hierarchy in Fault Collapsing (2005) (3)
Subthreshold voltage high-k CMOS devices have lowest energy and high process tolerance (2011) (3)
Bounds on Defect Level and Fault Coverage in Linear Analog Circuit Testing (2009) (3)
Eliminating the Timing Penalty of Scan (2013) (3)
Built-in Adaptive Test and Calibration of DAC (2009) (3)
Polynomial Coefficient Based Multi-Tone Testing of Analog Circuits (2009) (3)
Anomalies of dielectric-coated gratings. (1972) (3)
Delay Fault Testing : Present and Future (2019) (3)
Statistical Delay Fault Coverage Estimation for Synchronous Sequential Circuits (1998) (3)
Simulation of at-speed tests for stuck-at faults (1995) (3)
Characterizing Processors for Energy and Performance Management (2015) (3)
Delay independent initialization of sequential circuits (1994) (3)
Estimating stuck fault coverage in sequential logic using state traversal and entropy analysis (2007) (2)
Defect Diagnosis of Digital Circuits Using Surrogate Faults (2013) (2)
Grating lobe suppression in multiple access array of TDRSS spacecraft (1978) (2)
A diagnostic test generation system and a coverage metric (2010) (2)
Towards spatial fault resilience in array processors (2012) (2)
Compaction of Diagnostic Test Set for a Full-Response Dictionary (2009) (2)
Principal Component Analysis in Machine Intelligence-Based Test Generation (2021) (2)
Neural Network Guided Spatial Fault Resilience in Array Processors (2013) (2)
Diagnostic Test Generation for Transition Delay Faults Using Stuck-At Fault Detection Tools (2014) (2)
Comments on "Beamwidth of phased arrays" (1974) (2)
Specification test minimization for given defect level (2014) (2)
Sessionless SoC Test Scheduling With Frequency Scaling (2013) (2)
Functional test generation for non-scan sequential circuits (1995) (2)
Optimizing Tests for Multiple Fault Models (2007) (2)
VLSI design process (1985) (2)
Deterministic Versus Random Testing (1986) (2)
Optimizing logic design using Boolean transforms (1998) (2)
LNA Test: A Polynomial Coefficient Approach (2011) (2)
Analyzing Reconvergent Fanouts in Gate Delay Fault Simulation (2008) (2)
A Four-Transistor Level Converter for Dual-Voltage Low-Power Design (2014) (2)
Defect Characterization and Testing of Skyrmion-Based Logic Circuits (2021) (2)
Correlation Analysis of Compacted Test Vectors and the Use of Correlated Vectors for Test Generation (2007) (2)
Distinguishing process variation induced faults from manufacturing defects in analog circuits using V-transform coefficients (2011) (2)
Design for high-speed testability of stuck-at faults (1996) (1)
Verification of the Alpha-Power Law by a CMOS Inverter Chain S (2015) (1)
Enhancing random access scan for soft error tolerance (2010) (1)
Simulation on Multiprocessors (1994) (1)
A New ATPG Algorithm for 21 st Century : The Simplest But Powerful (2004) (1)
Optimal Selection of ATE Frequencies for Test Time Reduction Using Aperiodic Clock (2014) (1)
Fault modeling and test generation (1991) (1)
Few Good Frequencies for Power-Constrained Test (2015) (1)
Partial scan testing with single clock control (1993) (1)
Antitest � Exclusive Test � and Concurrent Test (2004) (1)
Stafan algorithms for MOS circuits (1991) (1)
SoC TAM Design to Minimize Test Application Time (2015) (1)
Graphical cmos i(ddq) testing signatures based on data mining (2003) (1)
Comments on "Characterization of the random array peak sidelobe" (1980) (1)
Multi-Heuristic Machine Intelligence Guidance in Automatic Test Pattern Generation (2022) (1)
A Review of Testing of Digital VLSI Devices (1985) (1)
Fault Coverage Estimation for Non-Random Functional Input Sequences (2006) (1)
Evaluating Impact of Soft errors in an Embedded System (2012) (1)
State and Fault Information for Compaction-Based Test Generation (2002) (1)
Computing bounds on dynamic power using fast zero-delay logic simulation (2009) (1)
Dictionary-Less Defect Diagnosis as Surrogate Single Stuck-At Faults (2013) (1)
Selecting ATE Frequencies for Power Constrained Test Time Reduction Using Aperiodic Clock (2014) (1)
A tutorial on test power (2008) (1)
Fault Modeling and Test Generation for Technology-Specific Defects of Skyrmion Logic Circuits (2022) (1)
Editorial (2018) (1)
Editorial (2006) (0)
Editorial (1995) (0)
Editorial (1999) (0)
Editorial (1998) (0)
Editorial (2018) (0)
Message from the LATS2015 Chairs (2015) (0)
Editorial (2002) (0)
History and Background: Digital Logic and Fault Simulation (1994) (0)
Editorial (2014) (0)
ATS 2019 Program Committee (2019) (0)
Editorial (2015) (0)
Subthreshold Voltage Operation of C 6288 at 45 nm technology (2015) (0)
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Editorial (1983) (0)
Data-Driven DPPM Estimation and Adaptive Fault Coverage Calibration Using MATLAB® (2012) (0)
Evolutionary Algorithms for Low Power Test Pattern Generator (2016) (0)
Concurrent Software Simulation (CSS) (1994) (0)
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Tance and Unit Wire Resistance. 3 (1993) (0)
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Testing of GALS Components (2018) (0)
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Testing in the fourth dimension (2000) (0)
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Panel: Increasing test coverage in a VLSI desgin course (1999) (0)
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Three-Stage Optimization of Pre-Bond Diagnosis of TSV Defects (2017) (0)
A United States Patent ( 19 ) 11 ) Patent Number : 5 , 519 , 713 Baeg et al . 45 ) Date of Patent : May 21 , 1996 54 INTEGRATED CIRCUIT HAVING (2017) (0)
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Diagnostic Test Generation and Fault Simulation Algorithms for Transition Faults (2011) (0)
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Practically Realizing Random Access Scan Practically Realizing Random Access Scan Practically Realizing Random Access Scan Practically Realizing Random Access Scan (2005) (0)
Test Programming for Power Constrained Devices (2013) (0)
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Editorial (2015) (0)
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Editorial (2016) (0)
Session details: Design optimization for low power (2010) (0)
Diagnostic Test Generation for Transition Delay Faults Using Stuck-At Fault Detection Tools (2014) (0)
Test technology educational program TTEP 2004 overview of tutorials of VTS 2004 (2004) (0)
Editorial (2013) (0)
Editorial (1999) (0)
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Editorial (2016) (0)
Parallel Processing Preliminaries (1991) (0)
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Editorial (2003) (0)
Simulated Neural Networks (1991) (0)
Tutorial Five Electronic Testing for SOC Designers (2002) (0)
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Editorial (2022) (0)
Editorial (1997) (0)
Min-Max Simulation (1994) (0)
Fault Simulation of Diagnostic Programs (1994) (0)
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Test technology educational program TTEP 2004 overview of tutorials of VTS 2004 (2004) (0)
Eliminating the Timing Penalty of Scan (2013) (0)
Logic Circuits and Testing (1991) (0)
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4 Near-optimal Routing Trees (1993) (0)
Technology Characterization Model and Scaling for Energy Management (2019) (0)
VLSID 2020 Committees (2020) (0)
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Collaboration between industry and academia in test research (2000) (0)
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Neural Modeling for Digital Circuits (1991) (0)
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Built-in Self-test of Logic Resources in Field Programmable Gate Arrays Using Partial Reconfiguration Built-in Self-test of Logic Resources in Field Programmable Gate Arrays Using Partial Reconfiguration Built-in Self-test of Logic Resources in Field Programmable Gate Arrays Using Partial Reconfigur (2006) (0)
An Algorithm for Diagnostic Fault Simulation ∗ ( Extended Summary ) (2009) (0)
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1995 Asian Test Symposium carves a niche (1996) (0)
Minimizing N -detect Tests for Combinational Circuits Minimizing N -detect Tests for Combinational Circuits Minimizing N -detect Tests for Combinational Circuits (2006) (0)
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1985 to 1987: My years with D&T (2004) (0)
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IEEE fellow nominations sought for 1994 (1994) (0)
Defect Level Constrained Optimization of Analog and Radio Frequency Specification Tests (2015) (0)
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A Maximum Power Algorithm to Find Frequencies for Aperiodic Clock Testing (2015) (0)
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Pharmacological Treatment and Prevention of Chronic Lung Disease in Preterm Infants (2010) (0)
Test Generation Reformulated (1991) (0)
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Author's reply (2015) (0)
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Applications of Mixed-Signal Technology in Digital Testing (2016) (0)
Diagnostic Test Set Minimization and Full-Response Fault Dictionary (2012) (0)
Neural Network Guided Spatial Fault Resilience in Array Processors (2013) (0)
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Session details: Managing process variability (2009) (0)
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Keynote Talk: A History of the VLSI Design Conference (2012) (0)
Defect Level Constrained Optimization of Analog and Radio Frequency Specification Tests (2015) (0)
VLSI Design 2007 Best Paper Awards Prof. Arun Kumar Chaudhury Best Paper Award (Tie between two papers) (2007) (0)
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Design and test-the two sides of a coin (1991) (0)
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STAFAN: An alternative to fault simulation (1984) (0)
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Theorems on Redundancy Identi cation (2003) (0)
VLSI Design 2003 Call for Papers (2002) (0)
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Table of Contents. (2017) (0)
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Science, Technology, and the Indian Society (1996) (0)
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Built-In Test and Calibration of DAC/ADC Using A Low-Resolution Dithering DAC ∗ (2008) (0)
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Panel: New Research Problems in the Emerging Test Technology (1995) (0)
Reviews and abstracts - Helix antenna for multiple acces of TDRSS spacecraft (1978) (0)
A Maximum Power Algorithm to Find Frequencies for Aperiodic Clock Testing (2015) (0)
VLSI Design 2004 Technical Program Committee (2004) (0)
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Editorial (2011) (0)
Editorial (1997) (0)
Data-Driven DPPM Estimation and Adaptive Fault Coverage Calibration Using MATLAB® (2012) (0)
Editorial (2015) (0)
Editorial (2013) (0)
Editorial (1993) (0)
Call for Contributions (2016) (0)
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Editorial (2012) (0)
High Fault Coverage Built-In Self-Test for 3 rd Generation Mobile Phone User (2004) (0)
Editorial (2002) (0)
Introduction to Neural Networks (1991) (0)
Electrostatic Analog for Finding Nonintersecting Paths (1979) (0)
Multi-List-Traversal (1994) (0)
Editorial (2019) (0)
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Editorial (2017) (0)
Power-Aware Optimization of SoC Test Schedules Using Voltage and Frequency Scaling (2017) (0)
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Editorial (2002) (0)
Editorial (2011) (0)
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Editorial (1987) (0)
VLSI Design Steering Committee (2002) (0)
Editorial (2013) (0)
Editorial (2020) (0)
Editorial (2016) (0)
Editorial (1992) (0)
Editorial (2021) (0)
A Novel Wafer Manipulation Method for Yield Improvement and Cost Reduction of 3D Wafer-on-Wafer Stacked ICs (2014) (0)
Complexity of Defe t Level Modeling using theClustering (2000) (0)
Editorial (2019) (0)
Editorial (2018) (0)
Editorial (2015) (0)
Editorial (2000) (0)
Editorial (2016) (0)
Editorial (2011) (0)
Architectural Power Management for Battery Lifetime Optimization in Portable Systems (2011) (0)
Editorial (2016) (0)
Editorial (1999) (0)
Improved Pseudo-Random Fault Coverage Through Inversions: a Study on Test Point Architectures (2020) (0)
Editorial (2001) (0)
Editorial (2012) (0)
Editorial (2015) (0)
Transitive Closure And Testing (1991) (0)
Solving Graph Problems (1991) (0)
Editorial (2011) (0)
Editorial (2015) (0)
Energy Efficient Power Distribution on Many-Core SoC (2019) (0)
Editorial (2020) (0)
A correlation matrix method of clock partitioning for sequential circuit testability (1999) (0)
Editorial (2022) (0)
Editorial (2014) (0)
Polynomial-time Testability (1991) (0)
Editorial (2020) (0)
Editorial (1999) (0)
Editorial (2003) (0)
Editorial (2019) (0)
Editorial (1999) (0)
Modeling and Test Generation for Combinational Hardware (2018) (0)
Special Cases of Hard Problems (1991) (0)
Message from the Steering Committee Chair (2020) (0)
Editorial (2010) (0)
Editorial (2011) (0)
Editorial (2012) (0)
Editorial (2014) (0)
Editorial (2009) (0)
Editorial (2013) (0)
STAFAN Takes a Middle Course (1985) (0)
Concurrent Fault Simulation (1994) (0)
Program committee (2007) (0)
PROJECTED AS THE SINGLE BIGGEST IMPEDIMENT FOR PERFORMANCE AND ENERGY IMPROVEMENT WITH DEVICE SCALING (2012) (0)
Editorial (2007) (0)
Editorial (2016) (0)
Parametric Fault Testing of Non-Linear Analog Circuits Based on Polynomial and V-Transform Coefficients (2012) (0)
Editorial (2018) (0)
Editorial (2020) (0)
Table of Contents (2014) (0)
Editorial (1993) (0)
Editorial (2010) (0)
Defect Level and Fault Coverage in Coefficient Based Analog Circuit Testing (2012) (0)
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Editorial (2022) (0)
2011 JETTA Reviewers (2012) (0)
Editorial (2018) (0)
Editorial (1993) (0)
Invited Address: Core Testing and the Core of Testing (1998) (0)
Editorial (2007) (0)
Editorial (2014) (0)
Editorial (2018) (0)
Conference Steering Committee (2010) (2010) (0)
Towards Unclonable System Design for Resource-Constrained Applications (2019) (0)
2015 JETTA Reviewers (2016) (0)
Editorial (2005) (0)
Editorial (2022) (0)
Electronic Testing for SOC Designers (Tutorial Abstract) (2002) (0)
Editorial (1997) (0)
Editorial (2016) (0)
LSl PRODUCT Q UALITY A ND F AULT C OVERAGE (1981) (0)
Editorial (2020) (0)

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