Vivienne Sze
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American electrical engineer and computer scientist
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Vivienne Szecomputer-science Degrees
Computer Science
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Computer Architecture
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Vivienne Szeengineering Degrees
Engineering
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Electrical Engineering
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Computer Science Engineering
Why Is Vivienne Sze Influential?
(Suggest an Edit or Addition)According to Wikipedia, Vivienne Sze is an American electrical engineer and computer scientist whose research focuses on low-power electronics and on the trade-offs between energy use and computing power in the combined design of software and hardware, for applications including video coding and deep neural networks. She is an associate professor in the Massachusetts Institute of Technology Department of Electrical Engineering and Computer Science, where she heads the Energy-Efficient Multimedia Systems Group.
Vivienne Sze's Published Works
Number of citations in a given year to any of this author's works
Total number of citations to an author for the works they published in a given year. This highlights publication of the most important work(s) by the author
Published Works
- Efficient Processing of Deep Neural Networks: A Tutorial and Survey (2017) (2168)
- Eyeriss: An Energy-Efficient Reconfigurable Accelerator for Deep Convolutional Neural Networks (2016) (1439)
- Eyeriss: A Spatial Architecture for Energy-Efficient Dataflow for Convolutional Neural Networks (2016) (1165)
- 14.5 Eyeriss: An energy-efficient reconfigurable accelerator for deep convolutional neural networks (2016) (805)
- Designing Energy-Efficient Convolutional Neural Networks Using Energy-Aware Pruning (2016) (567)
- Eyeriss v2: A Flexible Accelerator for Emerging Deep Neural Networks on Mobile Devices (2018) (507)
- NetAdapt: Platform-Aware Neural Network Adaptation for Mobile Applications (2018) (408)
- High Efficiency Video Coding (HEVC), Algorithms and Architectures (2014) (338)
- FastDepth: Fast Monocular Depth Estimation on Embedded Systems (2019) (201)
- High Throughput CABAC Entropy Coding in HEVC (2012) (198)
- Core Transform Design in the High Efficiency Video Coding (HEVC) Standard (2013) (166)
- Hardware for machine learning: Challenges and opportunities (2016) (154)
- DeeperLab: Single-Shot Image Parser (2019) (135)
- Efficient Processing of Deep Neural Networks (2020) (117)
- Technologies for Ultradynamic Voltage Scaling (2010) (113)
- Accelergy: An Architecture-Level Energy Estimation Methodology for Accelerator Designs (2019) (100)
- A method to estimate the energy consumption of deep neural networks (2017) (93)
- Using Dataflow to Optimize Energy Efficiency of Deep Neural Network Accelerators (2017) (91)
- Low-Power Impulse UWB Architectures and Circuits (2009) (90)
- A 249-Mpixel/s HEVC Video-Decoder Chip for 4K Ultra-HD Applications (2014) (72)
- Navion: A 2-mW Fully Integrated Real-Time Visual-Inertial Odometry Accelerator for Autonomous Navigation of Nano Drones (2018) (71)
- Eyeriss v2: A Flexible and High-Performance Accelerator for Emerging Deep Neural Networks (2018) (69)
- Towards closing the energy gap between HOG and CNN features for embedded vision (Invited paper) (2017) (51)
- A 0.7-V 1.8-mW H.264/AVC 720p Video Decoder (2009) (50)
- A 0.4-V UWB baseband processor (2007) (47)
- Cost and Coding Efficient Motion Estimation Design Considerations for High Efficiency Video Coding (HEVC) Standard (2013) (46)
- An Energy-Efficient Hardware Implementation of HOG-Based Object Detection at 1080HD 60 fps with Multi-Scale Support (2016) (45)
- Energy-efficient HOG-based object detection at 1080HD 60 fps with multi-scale support (2014) (40)
- Freely scalable and reconfigurable optical hardware for deep learning (2020) (38)
- Visual-Inertial Odometry on Chip: An Algorithm-and-Hardware Co-design Approach (2017) (38)
- Unified forward+inverse transform architecture for HEVC (2012) (38)
- Designing Hardware for Machine Learning: The Important Role Played by Circuit Designers (2017) (36)
- A Highly Parallel and Scalable CABAC Decoder for Next Generation Video Coding (2011) (34)
- A 249Mpixel/s HEVC video-decoder chip for Quad Full HD applications (2013) (32)
- How to Evaluate Deep Neural Network Processors: TOPS/W (Alone) Considered Harmful (2020) (32)
- Design Considerations for Efficient Deep Neural Networks on Processing-in-Memory Accelerators (2019) (32)
- Multicore Processing and Efficient On-Chip Caching for H.264 and Future Video Decoders (2009) (31)
- Navion: A Fully Integrated Energy-Efficient Visual-Inertial Odometry Accelerator for Autonomous Navigation of Nano Drones (2018) (30)
- A Deeply Pipelined CABAC Decoder for HEVC Supporting Level 6.2 High-Tier Applications (2014) (29)
- Parallel CABAC for low power video coding (2008) (29)
- A comparison of CABAC throughput for HEVC/H.265 VS. AVC/H.264 (2013) (26)
- FSMI: Fast computation of Shannon mutual information for information-theoretic mapping (2019) (26)
- Hardware for machine learning: Challenges and opportunities (2018) (22)
- Entropy Coding in HEVC (2014) (22)
- Memory cost vs. coding efficiency trade-offs for HEVC motion estimation engine (2012) (22)
- FAST: A Framework to Accelerate Super-Resolution Processing on Compressed Videos (2016) (22)
- An Energy Efficient Sub-Threshold Baseband Processor Architecture for Pulsed Ultra-Wideband Communications (2006) (21)
- Energy and area-efficient hardware implementation of HEVC inverse transform and dequantization (2014) (21)
- MLSys: The New Frontier of Machine Learning Systems (2019) (21)
- A 58.6mW real-time programmable object detector with multi-scale multi-object support using deformable parts model on 1920×1080 video at 30fps (2016) (21)
- A low-power 0.7-V H.264 720p video decoder (2008) (21)
- SysML: The New Frontier of Machine Learning Systems (2019) (20)
- Hardware-aware motion estimation search algorithm development for high-efficiency video coding (HEVC) standard (2012) (17)
- Parallel tools in HEVC for high-throughput processing (2012) (16)
- Introduction to the Special Issue on HEVC Extensions and Efficient HEVC Implementations (2016) (15)
- A 58.6 mW 30 Frames/s Real-Time Programmable Multiobject Detection Accelerator With Deformable Parts Models on Full HD $1920\times 1080$ Videos (2017) (15)
- Rotate intra block copy for still image coding (2015) (15)
- A high throughput CABAC algorithm using syntax element partitioning (2009) (14)
- Parallelization of CABAC transform coefficient coding for HEVC (2012) (13)
- A 2014 Mbin/s deeply pipelined CABAC decoder for HEVC (2014) (13)
- NetAdaptV2: Efficient Neural Architecture Search with Fast Super-Network Training and Architecture Optimization (2021) (13)
- An Architecture-Level Energy and Area Estimator for Processing-In-Memory Accelerator Designs (2020) (12)
- Measuring Saccade Latency Using Smartphone Cameras (2020) (10)
- A Fully Integrated Energy-Efficient H.265/HEVC Decoder With eDRAM for Wearable Devices (2017) (10)
- FAST: Free Adaptive Super-Resolution via Transfer for Compressed Videos (2016) (10)
- Low Power Depth Estimation of Rigid Objects for Time-of-Flight Imaging (2018) (10)
- Balancing Actuation and Computing Energy in Motion Planning (2020) (9)
- Joint algorithm-architecture optimization of CABAC to increase speed and reduce area cost (2011) (9)
- Searching for Efficient Multi-Stage Vision Transformers (2021) (8)
- A 58 . 6 mW Real-Time Programmable Object Detector with Multi-Scale Multi-Object Support Using Deformable Parts Model on 1920 x 1080 Video at 30 fps (2016) (8)
- Sparseloop: An Analytical, Energy-Focused Design Space Exploration Methodology for Sparse Tensor Accelerators (2021) (8)
- Low power depth estimation for time-of-flight imaging (2017) (8)
- Enabling Saccade Latency Measurements with Consumer-Grade Cameras (2018) (8)
- Depth Estimation of Non-Rigid Objects for Time-Of-Flight Imaging (2018) (7)
- Determination of Saccade Latency Distributions using Video Recordings from Consumer-grade Devices (2018) (6)
- High-Throughput Computation of Shannon Mutual Information on Chip (2019) (6)
- An Efficient and Continuous Approach to Information-Theoretic Exploration (2020) (6)
- Sparseloop: An Analytical Approach To Sparse Tensor Accelerator Modeling (2022) (6)
- Joint Algorithm-Architecture Optimization of CABAC (2012) (5)
- HEVC ALF decode complexity analysis and reduction (2011) (5)
- Eyeriss v 2 : A Flexible and High-Performance Accelerator for Emerging Deep Neural Networks (2018) (5)
- Parallel algorithms and architectures for low power video decoding (2010) (4)
- Digital Optical Neural Networks for Large-Scale Machine Learning (2020) (4)
- Efficient Computation of Map-scale Continuous Mutual Information on Chip in Real Time (2021) (3)
- Technologies for Ultradynamic Voltage Scaling Circuits such as logic cells, static random access memories, analog-digital converters and dc-dc converters can be used as building blocks for applications that can function efficiently over a wide range of supply voltages. (2010) (3)
- Depth Map Estimation of Dynamic Scenes Using Prior Depth Information (2020) (3)
- Low Power Adaptive Time-of-Flight Imaging for Multiple Rigid Objects (2019) (3)
- Memory-Efficient Gaussian Fitting for Depth Images in Real Time (2022) (2)
- Data Centers on Wheels: Emissions From Computing Onboard Autonomous Vehicles (2023) (2)
- A 249 Mpixel / s HEVC video-decoder chip for Quad Full HD applications Citation (2012) (2)
- Developing a Series of AI Challenges for the United States Department of the Air Force* (2022) (2)
- App-Based Saccade Latency and Directional Error Determination Across the Adult Age Spectrum (2021) (2)
- A fully-integrated energy-efficient H.265/HEVC decoder with eDRAM for wearable devices (2017) (2)
- Decoder Hardware Architecture for HEVC (2014) (1)
- Uncertainty from Motion for DNN Monocular Depth Estimation (2022) (1)
- Low-Power Impulse UWB Architectures and Circuits Pulsed ultrawide band provides the energy needed for a high data-rate battery-operated transceiver, and a low data-rate transceiver suitable for battery-less operation. (2009) (1)
- Architecture-Level Energy Estimation for Heterogeneous Computing Systems (2021) (1)
- An Energy-Efficient, Fully Integrated 1920x1080 H.265/HEVC Decoder with eDRAM (2017) (1)
- Domain-Specific Language Abstractions for Compression (2021) (1)
- Hardware for Machine Learning : Challenges and Opportunities ( Invited Paper ) (2017) (1)
- Joint Algorithm-Architecture Optimization of CABAC (2012) (0)
- App-based saccade latency and error determination across the adult age spectrum. (2020) (0)
- An Energy-efficient Digital Baseband Processor for Pulsed UWB Using Extreme Parallellization (2006) (0)
- SE4: ICs in PandemICs (2021) (0)
- Session 9 Overview: ML Processors From Cloud to Edge Machine Learning Subcommittee (2021) (0)
- A 58 . 6 mW 30 fps Real-Time Programmable Multi-Object Detection Accelerator with Deformable Parts Models on Full HD 1920 (2017) (0)
- Progress on photonic tensor processors based on time multiplexing and photoelectric multiplication (2021) (0)
- TOPS/W (alone) Considered Harmful (2020) (0)
- SIGMICRO: G: A Mutual Information Accelerator for Autonomous Robot Exploration (2020) (0)
- RAELLA: Reforming the Arithmetic for Efficient, Low-Resolution, and Low-Loss Analog PIM: No Retraining Required! (2023) (0)
- An Energy-Efficient Hardware Implementation of HOG-Based Object Detection at 1080HD 60 fps with Multi-Scale Support (2015) (0)
- Gemino: Practical and Robust Neural Compression for Video Conferencing (2022) (0)
- Efficient Computing for AI and Robotics (2020) (0)
- Freely scalable and reconfigurable optical hardware for deep learning (2021) (0)
- A 1116-027 A 58 . 6 mW 30 fps Real-Time Programmable Multi-Object Detection Accelerator with Deformable Parts Models on Full HD 19201080 Videos (2016) (0)
- A 58.6mW 30fps Real-Time Programmable Multi-Object Detection Accelerator with Deformable Parts Models on Full HD 1920×1080 Videos (2017) (0)
- EE2: Workshop on circuits for social good (2018) (0)
- An Ultra-Low-Power Digital Baseband for a Pulsed Ultra-Wideband Transceiver Using Extreme Parallellization (2005) (0)
- Entropy Coding in HEVC Citation (2014) (0)
- Individualized Tracking of Neurocognitive-State-Dependent Eye-Movement Features Using Mobile Devices (2022) (0)
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