Wayne W. C. Luk
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Computer Science
Wayne W. C. Luk's Degrees
- PhD Computer Science University of Manchester
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(Suggest an Edit or Addition)Wayne W. C. Luk's Published Works
Number of citations in a given year to any of this author's works
Total number of citations to an author for the works they published in a given year. This highlights publication of the most important work(s) by the author
Published Works
- Reconfigurable computing: architectures and design methods (2005) (422)
- Accuracy-Guaranteed Bit-Width Optimization (2006) (226)
- FP-BNN: Binarized neural network on FPGA (2018) (202)
- A comparison of CPUs, GPUs, FPGAs, and massively parallel processor arrays for random number generation (2009) (201)
- Gaussian random number generators (2007) (200)
- Axel: a heterogeneous cluster with FPGAs and GPUs (2010) (175)
- Wordlength optimization for linear digital signal processing (2003) (157)
- Comparing Three Heuristic Search Methods for Functional Partitioning in Hardware–Software Codesign (2002) (152)
- Pipeline vectorization (2001) (150)
- A hardware Gaussian noise generator using the Box-Muller method and its error analysis (2006) (138)
- Dynamic voltage scaling for commercial FPGAs (2005) (124)
- Performance Comparison of Graphics Processors to Reconfigurable Logic: A Case Study (2010) (123)
- Unifying bit-width optimisation for fixed-point and floating-point designs (2004) (119)
- Enhancing Relocatability of Partial Bitstreams for Run-Time Reconfiguration (2007) (118)
- The Impact of Pipelining on Energy per Operation in Field-Programmable Gate Arrays (2004) (115)
- Compilation tools for run-time reconfigurable designs (1997) (108)
- Reconfigurable acceleration for Monte Carlo based financial simulation (2005) (106)
- NeMo: A Platform for Neural Modelling of Spiking Neurons Using GPUs (2009) (103)
- Customizable elliptic curve cryptosystems (2005) (99)
- A Gaussian noise generator for hardware-based simulations (2004) (99)
- A hardware Gaussian noise generator using the Wallace method (2005) (96)
- Have GPUs made FPGAs redundant in the field of video processing? (2005) (96)
- F-CNN: An FPGA-based framework for training Convolutional Neural Networks (2016) (94)
- Automating production of run-time reconfigurable designs (1998) (89)
- Pebble: A Language for Parametrised and Reconfigurable Hardware Design (1998) (89)
- LARA: an aspect-oriented programming language for embedded systems (2012) (88)
- Adaptive Routing in Network-on-Chips Using a Dynamic-Programming Network (2011) (88)
- Modelling and optimising run-time reconfigurable systems (1996) (87)
- The Multiple Wordlength Paradigm (2001) (85)
- Floating-Point FPGA: Architecture and Modeling (2009) (84)
- FPGA Accelerated Simulation of Biologically Plausible Spiking Neural Networks (2009) (82)
- Synthesis and optimization of DSP algorithms (2004) (82)
- Comparing performance and energy efficiency of FPGAs and GPUs for high productivity computing (2010) (81)
- Pipeline vectorization for reconfigurable systems (1999) (81)
- Novel FPGA-based implementation of median and weighted median filters for image processing (2005) (80)
- Video Image Processing with the Sonic Architecture (2000) (78)
- Dimensionality Reduction in Controlling Articulated Snake Robot for Endoscopy Under Dynamic Active Constraints (2013) (77)
- Ziggurat-based hardware Gaussian random number generator (2005) (74)
- NeuroFlow: A General Purpose Spiking Neural Network Simulation Platform using Customizable Processors (2016) (73)
- Optimizing hardware function evaluation (2005) (70)
- Hierarchical segmentation schemes for function evaluation (2003) (69)
- Hardware Generation of Arbitrary Random Number Distributions From Uniform Distributions Via the Inversion Method (2007) (67)
- An energy and power consumption analysis of FPGA routing architectures (2009) (67)
- An Overview of Low-Power Techniques for Field-Programmable Gate Arrays (2008) (66)
- MiniBit: bit-width optimization via affine arithmetic (2005) (65)
- Virtual Embedded Blocks: A Methodology for Evaluating Embedded Elements in FPGAs (2006) (65)
- CUSTARD - a customisable threaded FPGA soft processor and tools (2005) (63)
- Design Optimizations for Tiled Partially Reconfigurable Systems (2011) (63)
- Automatic Accuracy-Guaranteed Bit-Width Optimization for Fixed and Floating-Point Systems (2007) (62)
- High-Performance Embedded Architecture and Compilation Roadmap (2007) (60)
- Optimizing CNN-Based Object Detection Algorithms on Embedded FPGA Platforms (2017) (59)
- Truncation noise in fixed-point SFGs [digital filters] (1999) (59)
- Optimum wordlength allocation (2002) (59)
- Hardware Implementation Trade-Offs of Polynomial Approximations and Interpolations (2008) (59)
- Parameterised floating-point arithmetic on FPGAs (2001) (58)
- A flexible hardware encoder for low-density parity-check codes (2004) (58)
- A Reconfigurable Computing Approach for Efficient and Scalable Parallel Graph Exploration (2012) (57)
- Cube: A 512-FPGA cluster (2009) (57)
- A Large-Scale Spiking Neural Network Accelerator for FPGA Systems (2012) (56)
- Leveraging FPGAs for Accelerating Short Read Alignment (2017) (56)
- High Quality Uniform Random Number Generation Using LUT Optimised State-transition Matrices (2007) (55)
- Floating-point bitwidth analysis via automatic differentiation (2002) (54)
- On-FPGA Communication Architectures and Design Factors (2006) (53)
- FPGA-Optimised Uniform Random Number Generators Using LUTs and Shift Registers (2010) (53)
- Binomial filters (1996) (52)
- Deep Neural Network Approximation for Custom Hardware (2019) (52)
- Heuristic datapath allocation for multiple wordlength systems (2001) (51)
- Truncation noise in fixed-point SFGs (1999) (50)
- Customising graphics applications: techniques and programming interface (2000) (50)
- The LUT-SR Family of Uniform Random Number Generators for FPGA Architectures (2013) (50)
- Non-Uniform Random Number Generation Through Piecewise Linear Approximations (2006) (49)
- A Karatsuba-Based Montgomery Multiplier (2010) (49)
- Fast custom instruction identification by convex subgraph enumeration (2008) (49)
- A framework for FPGA acceleration of large graph problems: Graphlet counting case study (2011) (49)
- Pipeline morphing and virtual pipelines (1997) (48)
- Memory access optimisation for reconfigurable systems (2001) (47)
- FPGA Accelerated Low-Latency Market Data Feed Processing (2009) (46)
- A mixed precision Monte Carlo methodology for reconfigurable accelerator systems (2012) (46)
- Bitwise optimised CAM for network intrusion detection systems (2005) (46)
- FPGA Designs with Optimized Logarithmic Arithmetic (2010) (45)
- Design space exploration with A Stream Compiler (2003) (45)
- High-throughput one-dimensional median and weighted median filters on FPGA (2009) (44)
- Automating Customisation of Floating-Point Designs (2002) (43)
- CHIPS: Custom Hardware Instruction Processor Synthesis (2008) (43)
- A Reconfigurable Platform for Real-Time Embedded Video Image Processing (2003) (43)
- MR Safe Robotic Manipulator for MRI-Guided Intracardiac Catheterization (2018) (43)
- Hardware Acceleration of Genetic Sequence Alignment (2013) (42)
- Hardware/software codesign: a systematic approach targeting data-intensive applications (2005) (42)
- Hierarchical Segmentation for Hardware Function Evaluation (2009) (41)
- FPGA-based Streaming Computation for Lattice Boltzmann Method (2007) (41)
- A high-level compilation toolchain for heterogeneous systems (2009) (40)
- Reconfigurable Acceleration of Short Read Mapping (2013) (40)
- Optimizing Instruction-set Extensible Processors under Data Bandwidth Constraints (2007) (39)
- FPGA-Based Smith-Waterman Algorithm: Analysis and Novel Design (2011) (38)
- A Real-Time Object Detection Accelerator with Compressed SSDLite on FPGA (2018) (37)
- Credit Risk Modelling using Hardware Accelerated Monte-Carlo Simulation (2008) (37)
- Optimizing CNN-based Segmentation with Deeply Customized Convolutional and Deconvolutional Architectures on FPGA (2018) (35)
- Accelerating solvers for global atmospheric equations through mixed-precision data flow engine (2013) (35)
- Run-Time Management of Dynamically Recongigurable Designs (1998) (35)
- A hardware Gaussian noise generator for channel code evaluation (2003) (35)
- SPREAD: A Streaming-Based Partially Reconfigurable Architecture and Programming Model (2013) (35)
- Compiling Ruby into FPGAs (1995) (35)
- Multivariate Gaussian Random Number Generation Targeting Reconfigurable Hardware (2008) (34)
- Accelerating SpMV on FPGAs by Compressing Nonzero Values (2015) (34)
- Domain-Specific Hybrid FPGA: Architecture and Floating Point Applications (2007) (33)
- Non-uniform Segmentation for Hardware Function Evaluation (2003) (33)
- Reconfigurable Architecture for Network Flow Analysis (2008) (33)
- Reconfigurable shape-adaptive template matching architectures (2002) (33)
- Optimum and heuristic synthesis of multiple word-length architectures (2005) (32)
- Synthesis of saturation arithmetic architectures (2003) (32)
- Computer System Design: System-on-Chip (2011) (32)
- Hardware Acceleration for an Accurate Stereo Vision System Using Mini-Census Adaptive Support Region (2014) (32)
- HArtes: Hardware-Software Codesign for Heterogeneous Multicore Platforms (2010) (32)
- A Framework for Developing Parameterised FPGA Libraries (1996) (31)
- Optimizing Logarithmic Arithmetic on FPGAs (2007) (31)
- Performance‐driven instrumentation and mapping strategies using the LARA aspect‐oriented programming approach (2016) (31)
- Harnessing Human Computation Cycles for the FPGA Placement Problem (2009) (31)
- Efficient reconfigurable design for pricing asian options (2010) (31)
- Evaluation of SystemC modelling of reconfigurable embedded systems (2005) (31)
- Automatic Generation and Optimisation of Reconfigurable Financial Monte-Carlo Simulations (2007) (30)
- FISH: Fast Instruction SyntHesis for Custom Processors (2012) (30)
- Reconfigurable elliptic curve cryptosystems on a chip (2005) (30)
- An Analytical Model Relating FPGA Architecture to Logic Density and Depth (2011) (30)
- On the use of programmable hardware and reduced numerical precision in earth‐system modeling (2015) (30)
- Framework and tools for run-time reconfigurable designs (2000) (30)
- An FPGA implementation of the simplex algorithm (2006) (30)
- Exploiting run-time reconfiguration in stencil computation (2012) (29)
- FPGA-based computation of free-form deformations in medical image registration (2003) (29)
- Towards Efficient Convolutional Neural Network for Domain-Specific Applications on FPGA (2018) (29)
- A synthesizable datapath-oriented embedded FPGA fabric (2007) (29)
- Computer-based tools for regular array design (1990) (29)
- Is high level synthesis ready for business? A computational finance case study (2014) (28)
- Application-specific customisation of multi-threaded soft processors (2006) (28)
- Towards an embedded biologically-inspired machine vision processor (2010) (28)
- SONIC-a plug-in architecture for video processing (1999) (27)
- F-E3D: FPGA-based Acceleration of an Efficient 3D Convolutional Neural Network for Human Action Recognition (2019) (27)
- Heterogeneous Systems for Energy Efficient Scientific Computing (2012) (27)
- Run-Time Integration of Reconfigurable Video Processing Systems (2007) (27)
- A fully-pipelined expectation-maximization engine for Gaussian Mixture Models (2012) (27)
- Ramethy: Reconfigurable Acceleration of Bisulfite Sequence Alignment (2015) (27)
- Accelerating Database Systems Using FPGAs: A Survey (2018) (27)
- Reconfigurable acceleration of genetic sequence alignment: A survey of two decades of efforts (2017) (27)
- Energy-Aware Optimisation for Run-Time Reconfiguration (2010) (27)
- A highly-efficient and green data flow engine for solving euler atmospheric equations (2014) (26)
- A Reconfigurable Engine for Real-Time Video Processing (1998) (26)
- An analytical model describing the relationships between logic architecture and FPGA density (2008) (26)
- Optimizing Floating Point Units in Hybrid FPGAs (2012) (26)
- A Comment on the Implementation of the Ziggurat Method (2005) (26)
- Run-Time Adaptive Flexible Instruction Processors (2002) (26)
- Power profiling and optimization for heterogeneous multi-core systems (2011) (25)
- Accelerating Seismic Computations Using Customized Number Representations on FPGAs (2009) (25)
- Customising Hardware Designs for Elliptic Curve Cryptography (2004) (25)
- Exploring reconfigurable architectures for explicit finite difference option pricing models (2009) (25)
- Memory Access Optimization and RAM Inference for Pipeline Vectorization (1999) (25)
- Reconfiguring Distributed Applications in FPGA Accelerated Cluster with Wireless Networking (2011) (25)
- Dynamic scheduling Monte-Carlo framework for multi-accelerator heterogeneous clusters (2010) (25)
- A DP-network for optimal dynamic routing in network-on-chip (2009) (24)
- Robust Software Partitioning with Multiple Instantiation (2012) (24)
- Towards efficient deep neural network training by FPGA-based batch-level parallelism (2019) (24)
- Sampling from the Multivariate Gaussian Distribution using Reconfigurable Hardware (2007) (23)
- Reconfigurable computing for augmented reality (1999) (23)
- FPGA-optimised high-quality uniform random number generators (2008) (23)
- Using Reconfigurable Hardware to Speed up Product Development and Performance (1995) (23)
- Hardware Acceleration for Machine Learning (2017) (23)
- Accelerating Quadrature Methods for Option Valuation (2009) (23)
- Inversion-based hardware gaussian random number generator: A case study of function evaluation via hierarchical segmentation (2006) (22)
- F-C3D: FPGA-based 3-dimensional convolutional neural network (2017) (22)
- Compiling policy descriptions into reconfigurable firewall processors (2003) (22)
- Detecting power attacks on reconfigurable hardware (2012) (22)
- Parametric Design for Reconfigurable Software-Defined Radio (2009) (22)
- Parallel FPGA-based all pairs shortest paths for sparse networks: A human brain connectome case study (2012) (22)
- Automating Elimination of Idle Functions by Run-Time Reconfiguration (2013) (21)
- Hardware architectures for Monte-Carlo based financial simulations (2006) (21)
- A Real-Time Tree Crown Detection Approach for Large-Scale Remote Sensing Images on FPGAs (2019) (21)
- Systematic serialisation of array-based architectures (1993) (21)
- A Domain Specific Language for Reconfigurable Path-based Monte Carlo Simulations (2007) (21)
- Interleaving behavioral and cycle-accurate descriptions for reconfigurable hardware compilation (2005) (21)
- Exploring Reconfigurable Architectures for Binomial-Tree Pricing Models (2008) (20)
- Combining Instruction Coding and Scheduling to Optimize Energy in System-on-FPGA (2006) (20)
- An integrated system for developing regular array designs (2001) (20)
- Design optimizations to improve placeability of partial reconfiguration modules (2009) (20)
- Instrumented Multi-Stage Word-Length Optimization (2007) (20)
- A declarative approach to incremental custom computing (1995) (20)
- Parameterized High Throughput Function Evaluation for FPGAs (2004) (20)
- Efficient Hardware Generation of Random Variates with Arbitrary Distributions (2006) (20)
- Riley-2: A flexible platform for codesign and dynamic reconfigurable computing research (1997) (20)
- Exploring Reconfigurable Architectures for Tree-Based Option Pricing Models (2009) (20)
- Optimal datapath allocation for multiple-wordlength systems (2000) (20)
- Structured hardware compilation of parallel programs (1994) (20)
- Combining optimizations in automated low power design (2010) (20)
- Mixed Precision Processing in Reconfigurable Systems (2011) (19)
- REFLECT: Rendering FPGAs to Multi-core Embedded Computing (2011) (19)
- High quality uniform random number generation through LUT optimised linear recurrences (2005) (19)
- Modeling post-techmapping and post-clustering FPGA circuit depth (2009) (19)
- Power adaptive computing system design in energy harvesting environment (2011) (19)
- Multiple precision for resource minimization (2000) (19)
- Automating Optimization of Reconfigurable Designs (2014) (19)
- Optimising Sparse Matrix Vector multiplication for large scale FEM problems on FPGA (2016) (18)
- Reconfigurable Control Variate Monte-Carlo Designs for Pricing Exotic Options (2010) (18)
- Stream Processing Dual-Track CGRA for Object Inference (2018) (18)
- Towards a declarative framework for hardware-software codesign (1994) (18)
- Automatic Optimising CNN with Depthwise Separable Convolution on FPGA: (Abstact Only) (2018) (18)
- Real-Time Anomaly Detection for Flight Testing Using AutoEncoder and LSTM (2019) (18)
- A partially reconfigurable architecture supporting hardware threads (2012) (18)
- Source-directed transformations for hardware compilation (2003) (18)
- Specifying Compiler Strategies for FPGA-based Systems (2012) (18)
- Heterogeneous Reconfigurable System for Adaptive Particle Filters in Real-Time Applications (2013) (18)
- Optimising Performance of Quadrature Methods with Reduced Precision (2012) (18)
- Roundoff-noise shaping in filter design (2000) (18)
- Controlling a complete hardware synthesis toolchain with LARA aspects (2013) (18)
- Optimising explicit finite difference option pricing for dynamic constant reconfiguration (2012) (18)
- High-Throughput Convolutional Neural Network on an FPGA by Customized JPEG Compression (2020) (18)
- Transparent insertion of latency-oblivious logic onto FPGAs (2014) (18)
- Optimizing Reconfigurable Recurrent Neural Networks (2020) (17)
- A hardware compilation flow for instance-specific VLIW cores (2008) (17)
- Hardware Design with a Scripting Language (2003) (17)
- The Coarse-Grained / Fine-Grained Logic Interface in FPGAs with Embedded Floating-Point Arithmetic Units (2008) (17)
- Optimising designs by combining model-based and pattern-based transformations (2009) (17)
- HARNESS Project: Managing Heterogeneous Computing Resources for a Cloud Platform (2014) (17)
- Parametric Encryption Hardware Design (2010) (17)
- Parameterized Function Evaluation for FPGAs (2001) (17)
- The derivation of regular synchronous circuits (1988) (17)
- Power-Adaptive Computing System Design for Solar-Energy-Powered Embedded Systems (2015) (16)
- A scalable design approach for stencil computation on reconfigurable clusters (2013) (16)
- A scalable hardware architecture for prime number validation (2004) (16)
- Mapping and scheduling with task clustering for heterogeneous computing systems (2008) (16)
- On-chip FPGA Debug Instrumentation for Machine Learning Applications (2019) (16)
- An efficient sparse conjugate gradient solver using a Beneš permutation network (2014) (16)
- FPGA based memory efficient high resolution stereo vision system for video tolling (2012) (16)
- Compilation and management of phase-optimized reconfigurable systems (2005) (16)
- Accelerating maximum likelihood estimation for Hawkes point processes (2013) (16)
- EURECA: On-Chip Configuration Generation for Effective Dynamic Data Access (2015) (16)
- A Systolic LRU Processor and Its Top-Down Development (1990) (16)
- Towards Hardware Accelerated Reinforcement Learning for Application-Specific Robotic Control (2018) (16)
- Customisable EPIC processor: architecture and tools (2004) (16)
- Parallel Genetic Algorithms on Multiple FPGAs (2016) (15)
- On Comparing Financial Option Price Solvers on FPGA (2011) (15)
- FPGA-based computation of free-form deformations (2002) (15)
- Solving the Global Atmospheric Equations through Heterogeneous Reconfigurable Platforms (2015) (15)
- Evaluating reconfigurable dataflow computing using the Himeno benchmark (2012) (15)
- An FPGA Architecture and CAD Flow Supporting Dynamically Controlled Power Gating (2016) (15)
- Scalable acceleration of inductive logic programs (2002) (15)
- PyHDL: Hardware Scripting with Python (2003) (15)
- Multi-level Customisation Framework for Curve Based Monte Carlo Financial Simulations (2012) (15)
- Integrated Hardware/Software Codesign for Heterogeneous Computing Systems (2008) (15)
- Power-Aware and Branch-Aware Word-Length Optimization (2008) (14)
- Chapter Four - Data Flow Computing in Geoscience Applications (2017) (14)
- Exploiting the chaotic behaviour of atmospheric models with reconfigurable architectures (2017) (14)
- Multiple-Wordlength Resource Binding (2000) (14)
- Tabu search with intensification strategy for functional partitioning in hardware-software codesign (2002) (14)
- Pipelining designs with loop-carried dependencies (2004) (14)
- Design Exploration of Quadrature Methods in Option Pricing (2012) (14)
- Reconfigurable Acceleration of 3D-CNNs for Human Action Recognition with Block Floating-Point Representation (2018) (14)
- Towards an Efficient Accelerator for DNN-Based Remote Sensing Image Segmentation on FPGAs (2019) (14)
- Mapping Large LSTMs to FPGAs with Weight Reuse (2020) (14)
- Efficient Weight Reuse for Large LSTMs (2019) (13)
- Automated placement of reconfigurable regions for relocatable modules (2010) (13)
- Reconfigurable Designs for Ray Tracing (2001) (13)
- Abstract 18568: Interfacing Fast Multi-phase Cardiac Image Registration with MRI-based Catheter Tracking for MRI-guided Electrophysiological Ablative Procedures (2014) (13)
- Optimizing FPGA-based vector product designs (1999) (13)
- Exploiting program branch probabilities in hardware compilation (2004) (13)
- Customising floating-point designs (2002) (13)
- Development framework for firewall processors (2002) (13)
- Design Validation by Symbolic Simulation and Equivalence Checking: A Case Study in Memory Optimization for Image Manipulation (2009) (13)
- Hardware Compilation of Deep Neural Networks: An Overview (2018) (13)
- Optimizing coarse-grained units in floating point hybrid FPGA (2008) (13)
- Branch Optimisation Techniques for Hardware Compilation (2003) (13)
- Flexible instruction processors (2000) (13)
- Compiling Hardware Descriptions with Relative Placement Information for Parametrised Libraries (2002) (13)
- MRI-based visual and haptic catheter feedback: simulating a novel system's contribution to efficient and safe MRI-guided cardiac electrophysiology procedures (2014) (13)
- FLiMS: Fast Lightweight Merge Sorter (2018) (13)
- Efficient Structured Pruning and Architecture Searching for Group Convolution (2018) (13)
- Static and Dynamic Reconfigurable Designs for a 2D Shape-Adaptive DCT (2000) (13)
- Quartz: a framework for correct and efficient reconfigurable design (2005) (12)
- Custom parallel caching schemes for hardware-accelerated image compression (2008) (12)
- A Heterogeneous Computing Framework for Computational Finance (2013) (12)
- Memory-Efficient Architecture for Accelerating Generative Networks on FPGA (2018) (12)
- Hardware acceleration of hidden Markov model decoding for person detection (2005) (12)
- PD-XML: extensible markup language for processor description (2002) (12)
- FASTER: Facilitating Analysis and Synthesis Technologies for Effective Reconfiguration (2012) (12)
- Compiling run-time parametrisable designs (2002) (12)
- Framework for Development and Distribution of Hardware Acceleration (2002) (12)
- Option pricing with multi-dimensional quadrature architectures (2009) (12)
- Implementation of Wave-Pipelined Interconnects in FPGAs (2008) (12)
- Parametric Optimization of Reconfigurable Designs Using Machine Learning (2013) (12)
- High-Performance FPGA Network Switch Architecture (2020) (12)
- FPGA acceleration of reference-based compression for genomic data (2015) (12)
- High-level language extensions for run-time reconfigurable systems (2003) (12)
- Dynamic clock-frequencies for FPGAs (2006) (12)
- Accelerating transfer entropy computation (2014) (12)
- A Fully-Pipelined Hardware Design for Gaussian Mixture Models (2017) (12)
- Real-time hardware acceleration of the trace transform (2007) (12)
- Systolic recursive filters (1988) (12)
- Accelerating Recurrent Neural Networks for Gravitational Wave Experiments (2021) (12)
- Automating custom-precision function evaluation for embedded processors (2005) (12)
- Customisable Hardware Compilation (2005) (12)
- Improving Performance Estimation for FPGA-Based Accelerators for Convolutional Neural Networks (2020) (11)
- A Hybrid Analog-Digital Routing Network for NoC Dynamic Routing (2007) (11)
- Dynamic Constant Reconfiguration for Explicit Finite Difference Option Pricing (2011) (11)
- Accelerating parameter estimation for multivariate self-exciting point processes (2014) (11)
- Exploring algorithmic trading in reconfigurable hardware (2010) (11)
- Wave-pipelined signaling for on-FPGA communication (2008) (11)
- Optimizing Finite Volume Method Solvers on Nvidia GPUs (2019) (11)
- Global interconnections in FPGAs: modeling and performance analysis (2008) (11)
- A Scalable Dataflow Accelerator for Real Time Onboard Hyperspectral Image Classification (2016) (11)
- FEM-based soft robotic control framework for intracavitary navigation (2017) (11)
- Constant power reconfigurable computing (2011) (11)
- Pipelined Genetic Propagation (2015) (11)
- Optimising designs by transposition (1991) (11)
- EXTRA: Towards the exploitation of eXascale technology for reconfigurable architectures (2016) (11)
- Memory Mapping for Multi-die FPGAs (2019) (11)
- CASK: Open-Source Custom Architectures for Sparse Kernels (2016) (11)
- Task-Parallel Programming of Reconfigurable Systems (2001) (11)
- Benchmarking Reconfigurable Architectures in the Mobile Domain (2009) (11)
- Architectures and Precision Analysis for Modelling Atmospheric Variables with Chaotic Behaviour (2015) (11)
- HW/SW partitioning for region-based dynamic partial reconfigurable FPGAs (2014) (11)
- Aspect driven compilation for dataflow designs (2013) (10)
- Accelerating Publish/Subscribe Matching on Reconfigurable Supercomputing Platforms (2010) (10)
- Accelerating radiosity calculations using reconfigurable platforms (2002) (10)
- Reconfigurable design with clock gating (2008) (10)
- Reconfigurable acceleration of microphone array algorithms for speech enhancement (2008) (10)
- Elastic Management of Reconfigurable Accelerators (2014) (10)
- A Hybrid Genetic-Programming Swarm-Optimisation Approach for Examining the Nature and Stability of High Frequency Trading Strategies (2014) (10)
- Reconfigurable filtered acceleration of short read alignment (2013) (10)
- Multiplierless Algorithm for Multivariate Gaussian Random Number Generation in FPGAs (2013) (10)
- Optimizing residue arithmetic on FPGAs (2008) (10)
- A New Approach to Control and Guide the Mapping of Computations to FPGAs (2011) (10)
- FPGA-based Acceleration of the Lattice Boltzmann Method (2007) (10)
- Comparing floating-point and logarithmic number representations for reconfigurable acceleration (2006) (10)
- Customised pearlmutter propagation: A hardware architecture for trust region policy optimisation (2017) (10)
- Estimation of sample mean and variance for Monte-Carlo simulations (2008) (10)
- Analysing parametrised designs by non-standard interpretation (1990) (10)
- Verification of streaming hardware and software codesigns (2012) (10)
- Low latency FPGA acceleration of market data feed arbitration (2014) (10)
- A Digit-Serial Structure for Reconfigurable Multipliers (2001) (10)
- A Flexible Multi-port Caching Scheme for Reconfigurable Platforms (2006) (10)
- A Self-Aware Tuning and Self-Aware Evaluation Method for Finite-Difference Applications in Reconfigurable Systems (2014) (10)
- A Structured Methodology for System-on-an-FPGA Design (2004) (10)
- Rapid Design Space visualisation through hardware/software partitioning (2009) (10)
- Customisable Control Policy Learning for Robotics (2019) (9)
- Benchmarking and evaluating reconfigurable architectures targeting the mobile domain (2010) (9)
- Resource efficient generators for the floating-point uniform and exponential distributions (2008) (9)
- ADAM: Automated Design Analysis and Merging for Speeding up FPGA Development (2018) (9)
- Knowledge Transfer in Automatic Optimisation of Reconfigurable Designs (2016) (9)
- Selected papers from the Oxford 1993 international workshop on field programmable logic and applications on More FPGAs (1994) (9)
- Adaptive Sequential Monte Carlo approach for real-time applications (2012) (9)
- Rapid estimation of power consumption for hybrid FPGAs (2008) (9)
- Proceedings of the 7th International Workshop on Field-Programmable Logic and Applications (1995) (9)
- Automatic optimisation of MapReduce designs by geometric programming (2009) (9)
- Automated framework for FPGA-based parallel genetic algorithms (2014) (9)
- Lossless Compression Decoders for Bitstreams and Software Binaries Based on High-Level Synthesis (2017) (9)
- Parallel neighbourhood search on many-core platforms (2013) (9)
- A Combined Approach to High-Level Synthesis for Dynamically Reconfigurable Systems (2000) (9)
- Solving Mesoscale Atmospheric Dynamics Using a Reconfigurable Dataflow Architecture (2017) (9)
- Programming framework for clusters with heterogeneous accelerators (2010) (9)
- Customisable architectures for the set covering problem (2013) (9)
- Image registration of real-time video data using the SONIC reconfigurable computer platform (2002) (9)
- Irregular Reconfigurable CAM Structures for Firewall Applications (2003) (9)
- Hardware Architectures for Adaptive Background Modelling (2007) (8)
- Hardware compilation for FPGAs: imperative and declarative approaches for a robotics interface (1993) (8)
- A Unified Codesign Run-Time Environment for the UltraSONIC Reconfigurable Computer (2003) (8)
- A Domain Specific Approach to High Performance Heterogeneous Computing (2015) (8)
- Convolution Based Spectral Partitioning Architecture for Hyperspectral Image Classification (2019) (8)
- Interconnection lengths and delays estimation for communication links in FPGAs (2008) (8)
- Using Statistical Assertions to Guide Self-Adaptive Systems (2014) (8)
- Application-specific customisation of market data feed arbitration (2013) (8)
- Retargeting a hardware compiler proof using protocol converters (1994) (8)
- Cluster-Driven Hardware/Software Partitioning and Scheduling Approach for a Reconfigurable Computer System (2003) (8)
- Quantum Chemistry in Dataflow: Density-Fitting MP2. (2017) (8)
- Accelerating sequential Monte Carlo method for real-time air traffic management (2013) (7)
- An Adaptable High-Throughput FPGA Merge Sorter for Accelerating Database Analytics (2020) (7)
- An Overlay for Rapid FPGA Debug of Machine Learning Applications (2019) (7)
- Optimizing FPGA-Based CNN Accelerator Using Differentiable Neural Architecture Search (2020) (7)
- Performance Estimation for Exascale Reconfigurable Dataflow Platforms (2018) (7)
- Multitasking in hardware-software codesign for reconfigurable computer (2003) (7)
- Profile-directed speculative optimization of reconfigurable floating point data paths (2007) (7)
- HARDWARE-ACCELERATED OBJECT TRACKING (2011) (7)
- Performance Tuning and Analysis for Stencil-Based Applications on POWER8 Processor (2018) (7)
- Dynamic Stencil: Effective exploitation of run-time resources in reconfigurable clusters (2013) (7)
- In-circuit temporal monitors for runtime verification of reconfigurable designs (2015) (7)
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- Automated Combination of Simulation and Hardware Prototyping (2004) (7)
- Using Reconfigurable Logic to Optimise GPU Memory Accesses (2008) (7)
- Customisable Multi-Processor Acceleration of Inductive Logic Programming (2011) (7)
- Quantitative Analysis of FPGA-based Database Searching (2001) (6)
- Autonomous Memory Block for reconfigurable computing (2004) (6)
- Towards Provably-Correct Hardware Compilation Tools Based on Pass Separation Techniques (2001) (6)
- Network-Level FPGA Acceleration of Low Latency Market Data Feed Arbitration (2015) (6)
- Optimising multi-loop programs for heterogeneous computing systems (2009) (6)
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- Combining imperative and declarative hardware descriptions (2003) (6)
- Is High Level Synthesis Ready for Business? An Option Pricing Case Study (2015) (6)
- Bridging the Gap between FPGAs and Multi-Processor Architectures: A Video Processing Perspective (2007) (6)
- Adaptive range reduction for hardware function evaluation (2004) (6)
- Accelerating the Merge Phase of Sort-Merge Join (2019) (6)
- FPGA-based acceleration of MRI registration: an enabling technique for improving MRI-guided cardiac therapy (2014) (6)
- Acceleration of real-time Proximity Query for dynamic active constraints (2013) (6)
- EXTRA: Towards an Efficient Open Platform for Reconfigurable High Performance Computing (2015) (6)
- An FPGA-specific algorithm for direct generation of multi-variate Gaussian random numbers (2010) (6)
- Mapping Adaptive Particle Filters to Heterogeneous Reconfigurable Systems (2015) (6)
- Automating qualification of reconfigurable cores (1999) (6)
- Static Block Floating-Point Quantization for Convolutional Neural Networks on FPGA (2019) (6)
- Pangloss: a novel Markov chain prefetcher (2019) (6)
- Reconfigurable acceleration of fitness evaluation in trading strategies (2015) (6)
- Acceleration of Short Read Alignment with Runtime Reconfiguration (2020) (6)
- Efficient Realtime FPGA Implementation of the Trace Transform (2006) (6)
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- Visualising reconfigurable libraries for FPGAs (1997) (6)
- Convolutional Neural Networks on Dataflow Engines (2017) (6)
- SMCGen: Generating Reconfigurable Design for Sequential Monte Carlo Applications (2014) (6)
- Parallel partitioning for distributed systems using sequential assignment (2013) (6)
- A general-purpose framework for FPGA-accelerated genetic algorithms (2015) (6)
- High quality uniform random number generation for massively parallel simulations in FPGA (2005) (6)
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- Reconfigurable designs for radiosity (2005) (6)
- A Reconfigurable Simulation Framework for Financial Computation (2006) (6)
- Parallelisation of Sequential Monte Carlo for real-time control in air traffic management (2013) (6)
- Pipelined reconfigurable accelerator for ordinal pattern encoding (2014) (6)
- Custom hardware architectures for posture analysis (2005) (6)
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- Reconfigurable computing: Productivity and performance (2009) (6)
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- Hardware/Software Codesign (2005) (5)
- Parametric reconfigurable designs with Machine Learning Optimizer (2012) (5)
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- The Effects of Polynomial Degrees (2005) (0)
- Reduction of design complexity using virtual hardware platforms (2004) (0)
- Pipelining and transposing heterogeneous array designs (1993) (0)
- FLiMS: A Fast Lightweight 2-Way Merger for Sorting (2021) (0)
- Designing with reconfigurability (2005) (0)
- A Unified Approach for Managing Heterogeneous Processing Elements on FPGAs (2022) (0)
- Exploring the potential of reconfigurable platforms for order book update (2017) (0)
- Acceleration of the Lattice Boltzmann Method for Fluid Flow (2007) (0)
- Maximising Parallel Memory Access for Low Latency FPGA Designs (2022) (0)
- Customization and Configurability (2011) (0)
- Appendix: Tools for Processor Evaluation (2011) (0)
- Hardware accelerated shaders using FPGA's (2008) (0)
- System Level Design Exploration of JPEG 2000 with SoftSONIC Virtual Hardware Platform (2006) (0)
- Remarn: A Reconfigurable Multi-threaded Multi-core Accelerator for Recurrent Neural Networks (2022) (0)
- Autonomous Memory Blocks : Scalable Structured Data Access for Reconfigurable Computing (2008) (0)
- Non-linear function evaluation reusing matrix-vector multipliers (2019) (0)
- High-Performance FPGA-based Accelerator for Bayesian Recurrent Neural Networks (2021) (0)
- Verified compilation of communicating processes into clocked circuits (1997) (0)
- Guest editors' introduction (1996) (0)
- Analytical Performance Estimation for Large-Scale Reconfigurable Dataflow Platforms (2021) (0)
- Distinguished Paper: Automated Combination of Simulation and Hardware Prototyping (2004) (0)
- Parallel processing on VLSI arrays: J.A. Nossek Kluwer Academic Publishers, Norwell, MA, 1991, 140 pp. US $65.00, £43.25, Dfl. 140.00 (1992) (0)
- AUTOMATIC ACCURACY-GUARANTEEDBIT-WIDTHOPTIMIZATION FOR FIXEDAND FLOATING-POINTSYSTEMS (2007) (0)
- 2013 8th International Workshop on Reconfigurable and Communication-Centric Systems-on-Chip (ReCoSoC), Darmstadt, Germany, July 10-12, 2013 (2013) (0)
- Designing Correct Circuits Paper: Serialising Heterogeneous and Non-Factorisable Processor Arrays (1996) (0)
- Systematically migrating an operational microphysics parameterisation to FPGA technology (2021) (0)
- Guest Editors' Introduction (2000) (0)
- From Tensor Algebra to Hardware Accelerators: Generating Streaming Architectures for Solving Partial Differential Equations (2018) (0)
- Modelling reconfigurable systems in event driven simulation (2012) (0)
- Event‐based high throughput computing: A series of case studies on a massively parallel softcore machine (2022) (0)
- MULTI-OBJECTIVE SELF-OPTIMIZATION OF RECONFIGURABLE DESIGNS WITH MACHINE LEARNING (2013) (0)
- A Partially Reconfigurable Architecture Supporting Hardware Threads (获FPT2012最佳论文提名) (2012) (0)
- Effective Reconfigurable Design: The FASTER Approach (2014) (0)
- RECONFIGURABLE SYSTEM FOR VIDEO PROCESSING (2005) (0)
- INTEGRATEDHARDWARE/SOFTWARE CODESIGNFOR HETEROGENEOUS COMPUTING SYSTEMS (2008) (0)
- Synthia: Synthesis of Interacting Automata Targeting LUT-based FPGAs (1999) (0)
- Optimum and Heuristic Synthesis of Multiple (2005) (0)
- RAW 2018 Invited Talks (2018) (0)
- In-circuit tuning of deep learning designs (2021) (0)
- A Customisable Multiprocessor for Application-Optimised Inductive Logic Programming (2008) (0)
- Automatic Generation of Application Specific Processor Libraries from a High Level Description (2006) (0)
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