William H. Robinson | Academic Influence

William H. Robinson's AcademicInfluence.com Rankings

William H. Robinson

Computer Science

#12172

World Rank

#12974

Historical Rank

Machine Learning

#5933

World Rank

#6030

Historical Rank

Artificial Intelligence

#6390

World Rank

#6504

Historical Rank

Database

#9951

World Rank

#10555

Historical Rank

computer-science Degrees

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Computer Science

William H. Robinson's Degrees

PhD Computer Science Stanford University
Masters Computer Science Stanford University
Bachelors Computer Science Stanford University

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Why Is William H. Robinson Influential?

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According to Wikipedia, William Hugh Robinson is an American engineer who is Professor of Electrical Engineering and Vice Provost for Academic at Vanderbilt University. His research considers sophisticated computer systems for consumer and industrial use. He is an advocate for improving access to engineering, and leads several investigations into programmes that better support people from marginalised groups.

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William H. Robinson's Published Works

Number of citations in a given year to any of this author's works

Total number of citations to an author for the works they published in a given year. This highlights publication of the most important work(s) by the author

Published Works

Characterization of Digital Single Event Transient Pulse-Widths in 130-nm and 90-nm CMOS Technologies (2007) (172)
On-Chip Characterization of Single-Event Transient Pulsewidths (2006) (141)
A distributed intrusion detection system for resource-constrained devices in ad-hoc networks (2010) (91)
Fault Simulation and Emulation Tools to Augment Radiation-Hardness Assurance Testing (2013) (85)
Characterizing SRAM Single Event Upset in Terms of Single and Multiple Node Charge Collection (2008) (84)
Securing commercial WiFi-based UAVs from common security attacks (2016) (82)
Modeling of Single Event Transients With Dual Double-Exponential Current Sources: Implications for Logic Cell Characterization (2015) (78)
Using Benchmarks for Radiation Testing of Microprocessors and FPGAs (2015) (76)
Effects of Guard Bands and Well Contacts in Mitigating Long SETs in Advanced CMOS Processes (2007) (67)
A low-power double edge-triggered flip-flop with transmission gates and clock gating (2010) (53)
Single-event mitigation in combinational logic using targeted data path hardening (2005) (40)
Impact of Supply Voltage and Frequency on the Soft Error Rate of Logic Circuits (2013) (40)
Filtergraph: An interactive web application for visualization of astronomy datasets (2013) (36)
Reliability-Aware Synthesis of Combinational Logic With Minimal Performance Penalty (2013) (35)
Resilient and efficient MANET aerial communications for search and rescue applications (2013) (27)
Design Comparison to Identify Malicious Hardware in External Intellectual Property (2011) (21)
Analysis of data-leak hardware Trojans in AES cryptographic circuits (2013) (20)
Aerial MANETs: Developing a Resilient and Efficient Platform for Search and Rescue Applications (2013) (19)
Impact of logic synthesis on soft error vulnerability using a 90-nm bulk CMOS digital cell library (2011) (19)
Using semi-supervised machine learning to address the Big Data problem in DNS networks (2017) (17)
Stealth assessment of hardware Trojans in a microcontroller (2012) (16)
Alternative Standard Cell Placement Strategies for Single-Event Multiple-Transient Mitigation (2014) (16)
A Passive Solution to the CPU Resource Discovery Problem in Cluster Grid Networks (2011) (16)
Constructing timing-based covert channels in mobile networks by adjusting CPU frequency (2014) (14)
The Effect of Negative Feedback on Single Event Transient Propagation in Digital Circuits (2006) (14)
Single-Event Multiple-Transient Characterization and Mitigation via Alternative Standard Cell Placement Methods (2015) (13)
Detection of Hardware Trojans in Third-Party Intellectual Property Using Untrusted Modules (2016) (13)
Soft Error Considerations for Multicore Microprocessor Design (2007) (13)
Embedded Intelligent Intrusion Detection: A Behavior-Based Approach (2007) (13)
Impact of Synthesis Constraints on Error Propagation Probability of Digital Circuits (2011) (12)
The Resource Usage Viewpoint of Industrial Control System Security: An Inference-Based Intrusion Detection System (2017) (11)
A Passive Solution to the Memory Resource Discovery Problem in Computational Clusters (2010) (11)
Using network traffic to verify mobile device forensic artifacts (2017) (11)
Fighting banking botnets by exploiting inherent command and control vulnerabilities (2014) (11)
Using Network Traffic to Remotely Identify the Type of Applications Executing on Mobile Devices (2013) (10)
Simulation Study on the Effect of Multiple Node Charge Collection on Error Cross-Section in CMOS Sequential Logic (2008) (10)
Exploiting Multi-Vendor Vulnerabilities as Back-Doors to Counter the Threat of Rogue Small Unmanned Aerial Systems (2018) (10)
An efficient technique to select logic nodes for single event transient pulse-width reduction (2013) (9)
Hardware Trojans: The defense and attack of integrated circuits (2011) (9)
Asynchronous Data Sampling Within Clock-Gated Double Edge-Triggered Flip-Flops (2013) (9)
Remotely inferring device manipulation of industrial control systems via network behavior (2015) (8)
Impact of Process Variations on Reliability and Performance of 32-nm 6T SRAM at Near Threshold Voltage (2014) (8)
Evaluation of Error Detection Strategies for an FPGA-Based Self-Checking Arithmetic and Logic Unit (2006) (8)
Fault Tolerance in MANETs Using a Task-to-Resource Reallocation Framework (2009) (8)
Fault-tolerant distributed reconnaissance (2010) (8)
Design of an Integrated Focal Plane Architecture for Efficient Image Processing (2002) (7)
Single-Event Characterization of Bang-bang All-digital Phase-locked Loops (ADPLLs) (2015) (6)
Network-based detection of mobile malware exhibiting obfuscated or silent network behavior (2018) (6)
Kernel-Based Circuit Partition Approach to Mitigate Combinational Logic Soft Errors (2014) (6)
A network-based approach to counterfeit detection (2013) (6)
Influence of Voltage and Particle LET on Timing Vulnerability Factors of Circuits (2015) (5)
Relative logic cell placement for mitigation of charge sharing-induced transients (2016) (4)
Using Network Traffic to Infer Hardware State (2015) (4)
Defending Against Consumer Drone Privacy Attacks: A Blueprint for a Counter Autonomous Drone Tool (2020) (4)
Using inherent command and control vulnerabilities to halt DDoS attacks (2015) (3)
A mobile two-way wireless covert timing channel suitable for peer-to-peer malware (2017) (3)
Timing analysis in software and hardware to implement NIST elliptic curves over prime fields (2013) (3)
The Use of Benchmarks for High-Reliability Systems (2015) (2)
A one Zener diode, one memristor crossbar architecture for a write-time-based PUF (2015) (2)
Pulse Broadening in Combinational Circuits with Standard Logic Cell Synthesis (2019) (2)
A Black Box Approach to Inferring, Characterizing, and Breaking Native Device Tracking Autonomy (2020) (2)
Characterizing SRAM Single Event Upset in Terms of Single and Double Node Charge Collection (2008) (2)
A CLOCK-GATED, DOUBLE EDGE-TRIGGERED FLIP-FLOP IMPLEMENTED WITH TRANSMISSION GATES (2011) (2)
Comparison of SEUTool results to experimental results in boeing radiation tolerant DSP (BDSP C30) (2005) (2)
Error Estimation and Error Reduction With Input-Vector Profiling for Timing Speculation in Digital Circuits (2019) (2)
Effects of Voltage and Temperature Variations on the Electrical Masking Capability of Sub-65 nm Combinational Logic Circuits (2018) (2)
A Dual-Threshold Voltage Approach for Timing Speculation in CMOS Circuits (2016) (2)
Cost modeling for early image processing applications (2001) (1)
Efficiency Analysis for a Mixed-Signal Focal Plane Processing Architecture (2005) (1)
ERSA – INVITED TALK/LECTURE Addressing the Challenges of Hardware Assurance in Reconfigurable Systems (2013) (1)
Electrical Masking Improvement with Standard Logic Cell Synthesis Using 45 nm Technology Node (2020) (1)
The effects of radiation-induced soft errors on hardware implementations of object-tracking algorithms (2017) (1)
Design-based variability in simulating single event transients (2016) (1)
Tattle Tail Security: An Intrusion Detection System for Medical Body Area Networks (MBAN) (2019) (1)
Privacy Violating Opensource Intelligence Threat Evaluation Framework: A Security Assessment Framework For Critical Infrastructure Owners (2020) (1)
THE EFFECT OF FREQUENCY AND TECHNOLOGY SCALING ON SINGLE EVENT VULNERABILITY OF THE COMBINATIONAL LOGIC UNIT IN THE LEON 2 SPARC V 8 PROCESSOR (2004) (1)
Impact of ion-induced transients on high-speed dual-complementary Flip-Flop designs (2011) (1)
Analysis of area-time efficiency for an integrated focal plane architecture (2003) (0)
Design and Analysis of Dual Edge Triggered D Flip-Flop (2020) (0)
On The Outside Looking In: Towards Detecting Counterfeit Devices Using Network Traffic Analysis (2017) (0)
Model-Based Analysis of Single-Event Upset (SEU) Vulnerability of 6T SRAM Using FinFET Technologies (2022) (0)
Modeling and implementation of an integrated pixel processing tile for focal plane systems (2003) (0)
Identification of Trojans in an FPGA using low-precision equipment (2014) (0)
Message from IWEC Workshop Co-chairs (2006) (0)
Soft ErrorConsiderations forMulticore MicroprocessorDesign (2007) (0)
IMIS 2011 Track Area Chairs Track 1: Smart Spaces and Intelligent Environments (2011) (0)
Bio-Inspired, Host-based Firewall (2020) (0)
RISK-AVERSION IN LABORATORY LEARNING (2013) (0)
EECE 277 FPGA Design (2005) (0)
Gem5Panalyzer: A Light-weight tool for Early-stage Architectural Reliability Evaluation & Prediction (2020) (0)
Understanding time-varying vulnerability accross GPU Program Lifetime (2022) (0)
Using Deep Learning to Identify Security Risks of Personal Mobile Devices in Enterprise Networks (2020) (0)

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Other Resources About William H. Robinson

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What Schools Are Affiliated With William H. Robinson?

William H. Robinson is affiliated with the following schools: