Wolfgang Nebel | Academic Influence

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Wolfgang Nebel

Computer Science

#1689

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#1750

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Computer Science

Wolfgang Nebel's Degrees

PhD Computer Science University of Kaiserslautern-Landau

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Why Is Wolfgang Nebel Influential?

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According to Wikipedia, Wolfgang Nebel is a German computer scientist and professor for integrated circuit design at the computer science department of the Carl von Ossietzky University of Oldenburg. Biography Nebel holds a Dipl.-Ing. degree in Electrical Engineering from the Leibniz University Hannover and a Dr.-Ing. degree from the Computer Science Department of the University of Kaiserslautern, where he has worked for Reiner Hartenstein. In 1987 Nebel joined Philips Semiconductors, Hamburg, and worked as software engineer, CAD project manager and finally became CAD software development manager. In 1993 he was appointed to the professorship VLSI design at the department of computer science at the Carl von Ossietzky University of Oldenburg. From 1996 to 1998 he served as dean of his department. Additionally since 1998 Nebel has been a member of the executive board of the OFFIS research center, an institute for information technology which is associated with Oldenburg University. From January 2001 December 2002 Nebel served as vice-president of Oldenburg University. Since June 2005 he has been chairman of the OFFIS – Institute for Information Technology. Nebel is co-founder, chairman and CTA of ChipVision Design Systems AG, an EDA start-up company located in Oldenburg, San Ramon, San Jose and Munich.

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Wolfgang Nebel's Published Works

Number of citations in a given year to any of this author's works

Total number of citations to an author for the works they published in a given year. This highlights publication of the most important work(s) by the author

Published Works

Low power design in deep submicron electronics (1997) (186)
Green IT: A Matter of Business and Information Systems Engineering? (2011) (88)
Estimation of lower and upper bounds on the power consumption from scheduled data flow graphs (2001) (54)
Leakage in CMOS Circuits - An Introduction (2004) (52)
System level optimization and design space exploration for low power (2001) (48)
Proceedings of the conference on Design, Automation and Test in Europe - Volume 3 (2001) (43)
OSSS+R: A framework for application level modelling and synthesis of reconfigurable systems (2009) (39)
Inheritance concept for signals in object-oriented extensions to VHDL (1995) (39)
Case study: system model of crane and embedded control (1999) (38)
The COMPLEX reference framework for HW/SW co-design and power management supporting platform-based design-space exploration (2013) (38)
Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation (2012) (37)
A new parameterizable power macro-model for datapath components (1999) (35)
Object-oriented hardware modelling-where to apply and what are the objects?' (1996) (32)
Proactive dynamic resource management in virtualized data centers (2011) (30)
Modeling Hard Real Time Systems with UML (1999) (29)
The Lower Saxony research network design of environments for ageing: towards interdisciplinary research on information and communication technologies in ageing societies (2010) (28)
Information and communication technologies for promoting and sustaining quality of life, health and self-sufficiency in ageing societies – outcomes of the Lower Saxony Research Network Design of Environments for Ageing (GAL) (2014) (27)
New approach in gate-level glitch modelling (1996) (26)
Non-invasive Power Simulation at System-Level with SystemC (2012) (25)
Short circuit power consumption of glitches (1996) (25)
Connecting SystemC-AMS models with OSCI TLM 2.0 models using temporal decoupling (2008) (25)
An ESL timing & power estimation and simulation framework for heterogeneous socs (2014) (25)
OSSS+R: Modelling and Simulating Self-Reconfigurable Systems (2006) (24)
SystemC-based Modelling, Seamless Refinement, and Synthesis of a JPEG 2000 Decoder (2008) (24)
Statistical static capacity management in virtualized data centers supporting fine grained QoS specification (2010) (22)
Designing for dynamic partially reconfigurable FPGAs with SystemC and OSSS (2004) (22)
System-level power optimization (2004) (22)
Modelling Macromodules for High-Level Dynamic Power Estimation of FPGA-based Digital Designs (2006) (21)
Power Macro-Modelling for Firm-Macro (2000) (19)
Memory power models for multilevel power estimation and optimization (2002) (19)
Motion Pattern Generation and Recognition for Mobility Assessments in Domestic Environments (2016) (18)
Towards an ESL Framework for Timing and Power Aware Rapid Prototyping of HW/SW Systems (2010) (17)
The Andres Project: Analysis and Design of Run-Time Reconfigurable, Heterogeneous Systems (2007) (17)
Power-simulation of cell based ASICs: accuracy- and performance trade-offs (1998) (16)
Using SystemC for an extended MATLAB/Simulink verification flow (2008) (15)
Behavioral model for cloud aware load and power management (2013) (15)
Data-and State-Dependent Power Characterisation and Simulation of Black-Box RTL IP Components at System Level (2014) (15)
The Quiny SystemC Front End: Self-Synthesising Designs (2006) (15)
Modelling the Impact of High Level Leakage Optimization Techniques on the Delay of RT-Components (2007) (14)
Analysis and Modeling of Subthreshold Leakage of RT-Components under PTV and State Variation (2006) (14)
Modelling control systems in SystemC AMS — Benefits and limitations (2009) (14)
Object-oriented modelling of parallel hardware systems (1998) (14)
A Unified Approach to Object-Oriented VHDL (1998) (13)
A flexible message passing mechanism for Objective VHDL (1998) (13)
RTL power modeling and estimation of sleep transistor based power gating (2007) (12)
Voltage- and ABB-island optimization in high level synthesis (2007) (12)
COMPLEX: COdesign and Power Management in PLatform-Based Design Space EXploration (2012) (12)
Automatic nonlinear memory power modelling (2001) (12)
Modeling and approaching a cost transparent, specific data center power consumption (2012) (12)
Behavioral-level thermal- and aging-estimation flow (2011) (11)
Leakage Models for High-Level Power Estimation (2018) (11)
Lower bounds on the power consumption in scheduled data flow graphs with resource constraints (2000) (11)
Lower and upper bounds an the switching activity in scheduled data flow graphs (1999) (10)
Power contracts: A formal way towards power-closure?! (2013) (10)
An Improved Power Macro-Model for Arithmetic Datapath Components (2002) (10)
A Novel Indoor Localization Approach Using Dynamic Changes in Ultrasonic Echoes (2012) (10)
Accurate PTV, State, and ABB Aware RTL Blackbox Modeling of Subthreshold, Gate, and PN-Junction Leakage (2006) (10)
RT level timing modeling for aging prediction (2016) (10)
Mixed-criticality system modelling with dynamic execution mode switching (2015) (10)
Efficient modelling and simulation of embedded software multi-tasking using SystemC and OSSS (2008) (10)
Modelling Program-State Machines in SystemC™ (2008) (10)
A quasi-cycle accurate timing model for binary translation based instruction set simulators (2016) (10)
Load dependent data center energy efficiency metric based on component models (2012) (9)
Gain More from PUE: Assessing Data Center Infrastructure Power Adaptability (2014) (9)
Advanced SystemC Tracing and Analysis Framework for Extra-Functional Properties (2015) (9)
Power and cost aware distributed load management (2010) (9)
Embedded tutorial: Analog-/mixed-signal verification methods for AMS coverage analysis (2016) (9)
Object oriented hardware design and synthesis based on systemC 2.0 (2003) (9)
JAVA VHDL-AMS, ADA Or C For System Level Specifications? (1999) (9)
Towards a synthesis semantics for SystemC channels (2010) (9)
Efficient NBTI modeling technique considering recovery effects (2014) (8)
Object-Oriented Specification and Design of Embedded Hard Real-Time Systems (2001) (8)
On the Verification of High-Order Constraint Compliance in IC Design (2008) (7)
Modelling Communication Interfaces with COMIX (2001) (7)
PolyDyn - Object-Oriented Modelling and Synthesis Targeting Dynamically Reconfigurable FPGAs (2010) (7)
System Specification Experiments on a Common Benchmark (2000) (6)
A workload extraction framework for software performance model generation (2015) (6)
A Data Center Simulation Framework Based on an Ontological Foundation (2014) (6)
ATM cell modelling using objective VHDL (1998) (6)
Interconnect Driven Low Power High-Level Synthesis (2003) (6)
Survey on Languages for Object Oriented Hardware Design Methodologies (1995) (6)
OSSS methodology - system-level design and synthesis of embedded HW/SW systems in C++ (2008) (6)
Transformation of event-driven HDL blocks for native integration into time-driven system models (2012) (6)
Towards Dependability-Aware Design of Hardware Systems Using Extended Program State Machines (2011) (6)
Automatic integration of hardware descriptions into system-level models (2012) (6)
Data Center Smart Grid Integration Considering Renewable Energies and Waste Heat Usage (2013) (6)
Analysis of NBTI effects on high frequency digital circuits (2016) (5)
Lower bound estimation for low power high-level synthesis (2000) (5)
High-level estimation and trade-off analysis for adaptive real-time systems (2009) (5)
Modeling of Embedded Software Multitasking in SystemC/OSSS (2008) (5)
High-Level Power Estimation and Analysis (2004) (5)
How to Avoid the Inheritance Anomaly in Ada (1998) (5)
Engineering and Management of Data Centers (2017) (5)
Objective VHDL: Hardware Reuse by Means of Object-Oriented Modeling (1997) (5)
Teaching Mixed-Criticality: Multi-Rotor Flight Control and Payload Processing on a Single Chip (2015) (5)
Early Power & Timing Estimation of Custom Hardware Blocks based on Automatically Generated Combinatorial Macros (2013) (5)
Challenges of multi- and many-core architectures for electronic system-level design (2011) (5)
Silicon Cochlea: a Digital VLSI Implementation of a Psychoacoustically and Physiologically Motivated Speech Preprocessor (1999) (4)
Using Early Power and Timing Estimations of Massively Heterogeneous Computation Platforms to Create Optimized HPC Applications (2014) (4)
Towards satisfaction checking of power contracts in Uppaal (2014) (4)
An automated flow for integrating hardware IP into the automotive systems engineering process (2009) (4)
Synthesizing Hardware from Object-Oriented Descriptions1 (1999) (4)
REX, automatic extraction of RT-level descriptions from integrated circuit layout data (1986) (4)
Considering variation and aging in a full chip design methodology at system level (2014) (4)
Expansion of Data Center's Energetic Degrees of Freedom to Employ Green Energy Sources (2014) (4)
Engineering and Management of Data Centers: An IT Service Management Approach (2017) (3)
A Compiler Comparison in the RISC-V Ecosystem (2020) (3)
Power Management Aware Low Leakage Behavioural Synthesis (2009) (3)
Data type analysis for hardware synthesis from object-oriented models (1999) (3)
Data Center Performance Model for Evaluating Load Dependent Energy Efficiency (2016) (3)
Evaluation of a Refinement-Driven SystemC"-Based Design Flow (2004) (3)
Exploration, Partitioning and Simulation of Reconfigurable Systems (Exploration, Partitionierung und Simulation rekonfigurierbarer Systeme) (2007) (3)
Phase Space Based NBTI Model (2012) (3)
Towards Probabilistic Timing Analysis for SDFGs on Tile Based Heterogeneous MPSoCs (2020) (3)
Generation of Binary Patterns with Given Spatiotemporal Correlations (1996) (3)
Logic design techniques for 65 to 45nm and below for reducing total energy and solving technology variations problems (2007) (3)
Power estimation at the logic level (1997) (3)
Inter cloud capable dynamic resource management with model of behavior (2013) (2)
Self-Adaptive Systems (2017) (2)
Hybrid logical-statistical simulation with thermal and IR-drop mapping for degradation and variation prediction (2009) (2)
Static/dynamic real-time legacy software migration: a comparative analysis (2020) (2)
Modeling communication with Objective VHDL (1998) (2)
Probabilistic State-Based RT-Analysis of SDFGs on MPSoCs with Shared Memory Communication (2019) (2)
Towards power management verification of time-triggered systems using virtual platforms (2018) (2)
Enabling energy-aware design decisions for behavioural descriptions containing black-box IP-components (2013) (2)
Modelling and Synthesis of Communication Using OSSS-Channels (2006) (2)
VHDL power simulator: power analysis at gate-level (1997) (2)
Functional Test Environment for Time-Triggered Control Systems in Complex MPSoCs Using GALI (2018) (2)
Work-in-Progress: Modeling of real-time communication for industrial distributed automation systems (2020) (2)
Auditory Signal Processing in Hardware: A Linear Gammatone Filterbank Design for a Model of the Auditory System (1999) (2)
User dependent aging prediction model for automotive controllers with power electronics (2017) (2)
Structural Contracts - Motivating Contracts to Ensure Extra-Functional Semantics (2015) (2)
A Task-Level Monitoring Framework for Multi-Processor Platforms (2016) (1)
Seamless design flow for reconfigurable systems. (2008) (1)
Implementing a quantitative model for the 'effective' signal processing in the auditory system on a dedicated digital VLSI hardware (1999) (1)
Real-Time Capable Retargeting of Xilinx MicroBlaze Binaries using QEMU: A Feasibility Study (2018) (1)
Automatic Transformation of System Models in Automotive Electronics (2009) (1)
SystemC-AMS SDF model synthesis for exploration of heterogeneous architectures (2010) (1)
Fast Propagation of Hamming and Signal Distances for Register-Transfer Level Datapaths (2012) (1)
Experimental Evaluation of Probabilistic Execution-Time Modeling and Analysis Methods for SDF Applications on MPSoCs (2019) (1)
Mobile Agents Based on Virtual Machines to Protect Sensitive Information (2014) (1)
Lower and Upper Bounds on the Switching Activity in Scheduled Data Flow Graphs 1 (1999) (1)
Predictable design of low power systems by pre-implementation estimation and optimization (2004) (1)
On Detecting Deadlocks in Large UML Models (2004) (1)
HW-Driven Emulation with Automatic Interface Generation (2003) (1)
Evaluating a system-based design flow (2004) (1)
Comparison of a RT and Behavioral Level Design Entry Regarding Power (2002) (1)
Abstract Hardware Modelling Using an Object-Oriented Language Extension to VHDL (1996) (1)
Early Power-Aware Design & Validation: Myth or Reality? (2007) (1)
Design Methods for Complex Digital Circuits (1989) (1)
A Functional Test Framework to Observe MPSoC Power Management Techniques in Virtual Platforms (2017) (1)
Exploration, Partitioning and Simulation of Reconfigurable (2007) (1)
Proceedings of the NATO Advanced Science Institute : Low Power Design in Deep Submicron Electronics, Il Ciocco, Italy, 20 - 30 Aug. 1996 (1997) (1)
Demand response and site management for cloud based Services (2012) (1)
An Integration Flow for Mixed-Critical Embedded Systems on a Flexible Time-Triggered Platform (2018) (1)
SPP1148 booth: Seamless design flow for reconfigurable systems (2008) (1)
Towards State-Based RT Analysis of FSM-SADFGs on MPSoCs with Shared Memory Communication (2017) (1)
Sleep-Transistor Based Power-Gating Tradeoff Analyses (2012) (1)
Digital Hearing Aids: Challenges and Solutions for Ultra Low Power (2005) (1)
An Advanced Simulink Verification Flow Using SystemC (2008) (0)
Proactive Workload Management for Bare Metal Deployment on Microservers (2018) (0)
Predicting Performance and Energy Efficiency for Large-Scale Parallel Applications on Highly Heterogeneous Platforms (2016) (0)
IDEA 2016: Integrating Dataflow, Embedded Computing, and Architecture (2017) (0)
Session details: Early power-aware design and validation: myth or reality? (2007) (0)
A Detailed Analysis of Timing Effects in an IEC 61499 Ethernet/TSN Communication Scenario (2022) (0)
Method and apparatus for optimizing power consumption in a data processing device (2006) (0)
Using IEC 61499 to Implement a Self-Organising Plug and Produce System (2018) (0)
Session details: Leakage analysis and optimization (2004) (0)
Multi-Tool Constraint Verification (2007) (0)
Digital circuit design with objective VHDL (2001) (0)
Reshaping EDA for power (2003) (0)
Proceedings : Design, Automation and Test in Europe, conference and exhibition 2001 : Munich, Germany, March 13-16, 2001 (2001) (0)
On leakage currents: sources and reduction for transistors, gates, memories and digital systems (2008) (0)
PATMOS 2002. Technical Program (2002) (0)
Final Event Overview (2015) (0)
Experiments on a Common Benchmark System (2000) (0)
Timing Contracts and Monitors for Safety Relevant Controller Design in IEC 61499 (2020) (0)
VHDL for high speed desktop video ICs: experience with replacement of other simulator (1992) (0)
DATE Executive Committee (2002) (0)
Impact of Data Sharing on Co-Running Embedded Applications in Multi-core System (2015) (0)
Synthesis Oriented Communication Design for Structural Hardware Objects (2001) (0)
Experimental Evaluation of Scenario Aware Synchronous Data Flow based Power Management (2019) (0)
A technology description method for generalized layout / circuit relations (1988) (0)
Energetic Data Center Design Considering Energy Efficiency Improvements During Operation (2017) (0)
Evaluation of a refinement-driven systemC/spl trade/-based design flow (2004) (0)
Abstraction NBTI model (2021) (0)
Timing modeling at RT-level by separation of design- and stress related aging impacts (2017) (0)
Qalitative and Quantitative Analysis of IC Designs (2008) (0)
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, DATE 2015, Grenoble, France, March 9-13, 2015 (2015) (0)
Impact of Array Data Flow Analysis on the Design of Energy-Efficient Circuits (2006) (0)
Optimization of Digital Audio Processing Algorithms Suitable for Hearing Aids (2005) (0)
Session details: Reshaping EDA for power (2003) (0)
A High Level Constant Coefficient Multiplier Power Model for Power Estimation on High Levels of Abstraction (2005) (0)
Reuse and Quality Estimation Prepared (2007) (0)
Proceedings of the conference on European design automation, EURO-DAC '92, Hamburg, Germany, September 7-10, 1992 (1996) (0)
A Timed-Value Stream Based ESL Timing and Power Estimation and Simulation Framework for Heterogeneous MPSoCs (2020) (0)
Legacy software migration based on timing contract aware real-time execution environments (2021) (0)
Considering VM migration between IaaS Clouds and mobile Clients: Challenges and Potentials (2014) (0)
Rapid Prototyping of Complex HW/SW Systems using a Timing and Power Aware ESL Framework (2012) (0)
A methodology for scaling power dissipation values between different FPGAs (2014) (0)
A Measurement-Based Message-Level Timing Prediction Approach for Data-Dependent SDFGs on Tile-Based Heterogeneous MPSoCs (2021) (0)
Proceedings of the 2006 International Symposium on Low Power Electronics and Design, 2006, Tegernsee, Bavaria, Germany, October 4-6, 2006 (2006) (0)
VHDL for high speed desktop video ICs-experience with replacement of other simulator (1992) (0)
ON DETECTING DEADLOCKS IN LARGE UML MODELS Based on an Expressive Subset (2005) (0)
Green-IT - Opportunities and Challenges (2009) (0)
Objective VHDL Requirements Collection and Design Objectives for object oriented extensions to VHDL (2007) (0)
A Timed-Value Stream Based ESL Timing and Power Estimation and Simulation Framework for Heterogeneous MPSoCs (2020) (0)

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