Yale Patt

Q: What Schools Are Affiliated With Yale Patt

Yale Patt is affiliated with the following schools: University of California, Berkeley, University of Texas at Austin, University of Michigan, Stanford University, Cornell University, Northeastern University, San Francisco State University

Yale Patt's AcademicInfluence.com Rankings

Yale Patt

Computer Science

#299

World Rank

#311

Historical Rank

#171

USA Rank

Computer Architecture

World Rank

Historical Rank

USA Rank

Database

#1584

World Rank

#1662

Historical Rank

#409

USA Rank

computer-science Degrees

Yale Patt

Engineering

#188

World Rank

#364

Historical Rank

#88

USA Rank

Electrical Engineering

#85

World Rank

#98

Historical Rank

#39

USA Rank

engineering Degrees

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Computer Science
Engineering

Yale Patt's Degrees

PhD Electrical Engineering Stanford University
Masters Electrical Engineering Stanford University
Bachelors Electrical Engineering University of California, Berkeley

Why Is Yale Patt Influential?

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According to Wikipedia, Yale Nance Patt is an American professor of electrical and computer engineering at The University of Texas at Austin. He holds the Ernest Cockrell, Jr. Centennial Chair in Engineering. In 1965, Patt introduced the WOS module, the first complex logic gate implemented on a single piece of silicon. He is a fellow of both the Institute of Electrical and Electronics Engineers and the Association for Computing Machinery, and in 2014 he was elected to the National Academy of Engineering.

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Yale Patt's Published Works

Number of citations in a given year to any of this author's works

Total number of citations to an author for the works they published in a given year. This highlights publication of the most important work(s) by the author

Published Works

Utility-Based Cache Partitioning: A Low-Overhead, High-Performance, Runtime Mechanism to Partition Shared Caches (2006) (1021)
Adaptive insertion policies for high performance caching (2007) (711)
Two-level adaptive training branch prediction (1991) (528)
Runahead execution: an alternative to very large instruction windows for out-of-order processors (2003) (449)
A Comparison Of Dynamic Branch Predictors That Use Two Levels Of Branch History (1993) (427)
Improving GPU performance via large warps and two-level warp scheduling (2011) (418)
Alternative Implementations of Two-Level Adaptive Branch Prediction (1993) (390)
Feedback Directed Prefetching: Improving the Performance and Bandwidth-Efficiency of Hardware Prefetchers (2007) (328)
A Case for MLP-Aware Cache Replacement (2006) (324)
Accelerating Critical Section Execution with Asymmetric Multicore Architectures (2009) (318)
Scheduling algorithms for modern disk drives (1994) (318)
Fairness via source throttling: a configurable and high-performance fairness substrate for multi-core memory systems (2010) (302)
Alternative implementations of two-level adaptive branch prediction (1992) (300)
Simultaneous subordinate microthreading (SSMT) (1999) (256)
On-line extraction of SCSI disk drive parameters (1995) (229)
The V-Way cache: demand-based associativity via global replacement (2005) (227)
Feedback-driven threading: power-efficient and high-performance execution of multi-threaded workloads on CMPs (2008) (205)
Hierarchical Data Format (2011) (197)
Coordinated control of multiple prefetchers in multi-core systems (2009) (193)
Prefetch-Aware DRAM Controllers (2008) (180)
Single instruction stream parallelism is greater than two (1991) (176)
Decision Procedures for Surjectivity and Injectivity of Parallel Maps for Tessellation Structures (1972) (173)
The Agree Predictor: A Mechanism For Reducing Negative Branch History Interference (1997) (172)
Branch Classification: A New Mechanism for Improving Branch Predictor Performance (1994) (171)
Checkpoint repair for out-of-order execution machines (1987) (162)
Using Hybrid Branch Predictors to Improve Branch Prediction Accuracy in the Presence of Context Switches (1996) (162)
Bottleneck identification and scheduling in multithreaded applications (2012) (162)
Target Prediction For Indirect Jumps (1997) (155)
Techniques for bandwidth-efficient prefetching of linked data structures in hybrid prefetching systems (2009) (155)
Prefetch-aware shared-resource management for multi-core systems (2011) (152)
Parallel application memory scheduling (2011) (150)
Metadata update performance in file systems (1994) (150)
HPS, a new microarchitecture: rationale and introduction (1985) (149)
Soft updates: a solution to the metadata update problem in file systems (2000) (142)
On pipelining dynamic instruction scheduling logic (2000) (137)
Increasing the instruction fetch rate via multiple branch prediction and a branch address cache (1993) (133)
One Billion Transistors, One Uniprocessor, One Chip (1997) (129)
Improving memory Bank-Level Parallelism in the presence of prefetching (2009) (128)
Disk arrays: high-performance, high-reliability storage subsystems (1994) (127)
Putting the fill unit to work: dynamic optimizations for trace cache microprocessors (1998) (124)
Checkpoint Repair for High-Performance Out-of-Order Execution Machines (1987) (122)
DRAM-Aware Last-Level Cache Writeback: Reducing Write-Caused Interference in Memory Systems (2010) (118)
Select-free instruction scheduling logic (2001) (116)
An analysis of correlation and predictability: what makes two-level branch predictors work (1998) (116)
Techniques for efficient processing in runahead execution engines (2005) (107)
Improving branch prediction accuracy by reducing pattern history table interference (1996) (102)
Predicting Performance Impact of DVFS for Realistic Memory Systems (2012) (99)
Runahead Execution: An Effective Alternative to Large Instruction Windows (2003) (98)
MorphCore: An Energy-Efficient Microarchitecture for High Performance ILP and High Throughput TLP (2012) (96)
Alternative implementations of hybrid branch predictors (1995) (95)
A Comprehensive Instruction Fetch Mechanism For A Processor Supporting Speculative Execution (1992) (95)
Accelerating Dependent Cache Misses with an Enhanced Memory Controller (2016) (91)
Utility-based acceleration of multithreaded applications on asymmetric CMPs (2013) (90)
Continuous runahead: Transparent hardware acceleration for memory intensive workloads (2016) (90)
Hardware Support For Large Atomic Units in Dynamically Scheduled Machines (1988) (87)
Line Distillation: Increasing Cache Capacity by Filtering Unused Words in Cache Lines (2007) (82)
Performance studies of a Prolog machine architecture (1985) (81)
Alternative fetch and issue policies for the trace cache fetch mechanism (1997) (72)
Using System-Level Models to Evaluate I/O Subsystem Designs (1998) (70)
Efficient Runahead Execution: Power-Efficient Memory Latency Tolerance (2006) (68)
Critical issues regarding HPS, a high performance microarchitecture (1985) (66)
Variable length path branch prediction (1998) (66)
Utility-Based Cache Partitioning (2006) (64)
Feedback-directed pipeline parallelism (2010) (64)
Microarchitecture-based introspection: a technique for transient-fault tolerance in microprocessors (2005) (63)
The effect of speculatively updating branch history on branch prediction accuracy, revisited (1994) (62)
Disk subsystem load balancing: disk striping vs. conventional data placement (1993) (58)
Improving trace cache effectiveness with branch promotion and trace packing (1998) (57)
Balancing I/O response time and disk rebuild time in a RAID5 disk array (1993) (54)
Address-value delta (AVD) prediction: increasing the effectiveness of runahead execution by exploiting regular memory allocation patterns (2005) (52)
Difficult-path branch prediction using subordinate microthreads (2002) (52)
VPC prediction: reducing the cost of indirect branches via hardware-based dynamic devirtualization (2007) (51)
An Investigation Of The Performance Of Various Dynamic Scheduling Techniques (1992) (50)
Exploiting fine-grained parallelism through a combination of hardware and software techniques (1991) (50)
Hierarchical registers for scientific computers (1988) (50)
Partitioned first-level cache design for clustered microarchitectures (2003) (49)
Increasing the Instruction Fetch Rate via Block-Structured Instruction Set Architectures (1996) (48)
Wish branches: combining conditional branching and predication for adaptive predicated execution (2005) (45)
Evaluation of Design Options for the Trace Cache Fetch Mechanism (1999) (44)
Facilitating superscalar processing via a combined static/dynamic register renaming scheme (1994) (43)
Flexible reference-counting-based hardware acceleration for garbage collection (2009) (43)
Introduction to computing systems - from bits and gates to C and beyond (2. ed.) (1999) (42)
The effects of mispredicted-path execution on branch prediction structures (1996) (41)
HPSm, a high performance restricted data flow architecture having minimal functionality (1986) (40)
Achieving Out-of-Order Performance with Almost In-Order Complexity (2008) (40)
The I/O Subsystem - A Candidate for Improvement: Guest Editor's Introduction (1994) (39)
Data marshaling for multi-core architectures (2010) (38)
Reducing the performance impact of instruction cache misses by writing instructions into the reservation stations out-of-order (1997) (36)
The process-flow model: examining I/O performance from the system's point of view (1993) (36)
Design decisions influencing the microarchitecture for a Prolog machine (1984) (36)
On Reusing the Results of Pre-Executed Instructions in a Runahead Execution Processor (2005) (35)
Improving the performance of object-oriented languages with dynamic predication of indirect jumps (2008) (34)
Set-Dueling-Controlled Adaptive Insertion for High-Performance Caching (2008) (34)
The I/O subsystem/spl minus/a candidate for improvement (1994) (34)
Diverge-Merge Processor (DMP): Dynamic Predicated Execution of Complex Control-Flow Graphs Based on Frequently Executed Paths (2006) (33)
Report of the Purdue Workshop on Grand Challenges in Computer Architecture for the Support of High Performance Computing (1992) (31)
Prefetch-Aware Memory Controllers (2011) (30)
Proceedings 29th Annual International Symposium on Computer Architecture (2002) (28)
Understanding the effects of wrong-path memory references on processor performance (2004) (27)
Variable length tree structures having minimum average search time (1969) (26)
Scheduling for Modern Disk Drives and Non-Random Workloads (2001) (26)
Filtered runahead execution with a runahead buffer (2015) (24)
Wrong Path Events: Exploiting Unusual and Illegal Program Behavior for Early Misprediction Detection and Recovery (2004) (23)
Requirements, bottlenecks, and good fortune: agents for microprocessor evolution (2001) (23)
Microarchitecture, compilers and algorithms (1996) (23)
Address-Value Delta (AVD) Prediction: A Hardware Technique for Efficiently Parallelizing Dependent Cache Misses (2006) (21)
Enhancing instruction scheduling with a block-structured ISA (1995) (21)
Branch history table indexing to prevent pipeline bubbles in wide-issue superscalar processors (1993) (21)
An analysis of the performance impact of wrong-path memory references on out-of-order and runahead execution processors (2005) (21)
HPSm, a high performance restricted data flow architecture having minimal functionality (1998) (20)
Energy Savings via Dead Sub-Block Prediction (2012) (20)
Fairness via Source Throttling: A Configurable and High-Performance Fairness Substrate for Multicore Memory Systems (2012) (19)
Single-Threaded vs. Multithreaded: Where Should We Focus? (2007) (18)
Microarchitectural support for precomputation microthreads (2002) (18)
Performance benefits of large execution atomic units in dynamically scheduled machines (1989) (17)
Asymmetric Chip Multiprocessors: Balancing Hardware Effic iency and Programmer Efficiency (2007) (17)
Run-time generation of HPS microinstructions from a VAX instruction stream (1986) (17)
Using the First-Level Caches as Filters to Reduce the Pollution Caused by Speculative Memory References (2005) (16)
Tailored Page Sizes (2020) (16)
Some Clarifications of the Concept of a Garden-of-Eden Configuration (1975) (15)
Profile-assisted Compiler Support for Dynamic Predication in Diverge-Merge Processors (2007) (15)
Recovery requirements of branch prediction storage structures in the presence of mispredicted-path execution (1997) (15)
Handling of packet dependencies: a critical issue for highly parallel network processors (2002) (15)
The Aquarius Project (1984) (14)
2D-profiling: detecting input-dependent branches with a single input data set (2006) (14)
Cache filtering techniques to reduce the negative impact of useless speculative memory references on processor performance (2004) (14)
Virtual Program Counter (VPC) Prediction: Very Low Cost Indirect Branch Prediction Using Conditional Branch Prediction Hardware (2009) (14)
Unification Parallelism: How Much Can We Exploit? (1989) (14)
Aquarius - A High Performance Computing System for Symbolic/Numeric Applications (1985) (14)
Comparing rebuild algorithms for mirrored and RAID5 disk arrays (1993) (13)
Retrospective: alternative implementations of two-level adaptive training branch prediction (1998) (13)
Compiling Prolog into microcode: a case study using the NCR/32-000 (1985) (13)
Yoga: A Hybrid Dynamic VLIW/OoO Processor (2014) (13)
A complex logic module for the synthesis of combinational switching circuits (1967) (12)
Advantages of Implementing PROLOG by Microprogramming a Host General Purpose Computer (1987) (12)
Dynamic Predication of Indirect Jumps (2007) (11)
Using non-volatile storage to improve the reliability of RAID5 disk arrays (1997) (11)
Author retrospective for increasing the instruction fetch rate via multiple branch prediction and a branch address cache (2014) (11)
The effect of real data cache behavior on the performance of a microarchitecture that supports dynamic scheduling (1991) (11)
BranchNet: A Convolutional Neural Network to Predict Hard-To-Predict Branches (2020) (11)
Optimal and Near-Optimal Universal Logic Modules with Interconnected External Terminals (1973) (10)
DESIGN CHOICES FOR THE HPSm MICROPROCESSOR CHIP. (1987) (10)
Using internal redundant representations and limited bypass to support pipelined adders and register files (2002) (10)
Wish Branches: Enabling Adaptive and Aggressive Predicated Execution (2006) (10)
PUP: An Architecture to Exploit Parallel Unification in Prolog (1988) (9)
CMOS CHIP FOR PROLOG. (1987) (9)
The use of microcode instrumentation for development, debugging and tuning of operating system kernels (1988) (9)
C COMPILER FOR HPS I, A HIGHLY PARALLEL EXECUTION ENGINE. (1986) (9)
SafeGuard: Reducing the Security Risk from Row-Hammer via Low-Cost Integrity Protection (2022) (8)
An Area-Efficient Register Alias Table for Implementing HPS (1990) (8)
Performance-aware speculation control using wrong path usefulness prediction (2008) (8)
Efficient runahead execution processors (2006) (8)
DRAM-Aware Last-Level Cache Replacement (2010) (8)
A High Performance Prolog Processor With Multiple Function Units (1989) (7)
Programming early considered harmful (2001) (7)
The implementation of Prolog via VAX 8600 microcode (1986) (7)
Alternative implementations of Prolog: the microarchitecture perspective (1989) (7)
Introduction to Computing Systems: From Bits & Gates to C & Beyond (2019) (7)
Alternative proposals for implementing Prolog concurrently and implications regarding their respective microarchitectures (1984) (7)
An experimental single-chip data flow CPU (1990) (7)
EXTENDING A PROLOG MACHINE FOR PARALLEL EXECUTION. (1986) (6)
Aquarius (1987) (6)
Improving the performance of UCSD Pascal via microprogramming on the PDP-11/60 (1983) (6)
A comparative performance evaluation of various state maintenance mechanisms (1993) (6)
Diverge-Merge Processor: Generalized and Energy-Efficient Dynamic Predication (2007) (6)
Top Picks [Guest editors' introduction] (2011) (6)
HPS IMPLEMENTATION OF VAX; INITIAL DESIGN AND ANALYSIS. (1986) (6)
Experimental Research in Computer Architecture - Guest Editor's Introduction to the Special Issue (1991) (5)
Education in computer science and computer engineering starts with computer architecture (1996) (5)
Dynamically Sizing the TAGE Branch Predictor (2016) (5)
On tuning the microarchitecture of an HPS implementation of the VAX (1987) (5)
Data Marshaling for Multicore Systems (2011) (5)
Trading disk capacity for performance (1993) (5)
Scheduling Algorithms for Modern Disk Drives (1994) (5)
Demand-Only Broadcast: Reducing Register File and Bypass Power in Clustered Execution Cores (2004) (4)
On tuning the microarchitecture of an HPS implementation of the VAX (1988) (4)
CLARIFICATION OF THE DYNAMIC/STATIC INTERFACE. (1987) (4)
A microcode-based environment for noninvasive performance analysis (1986) (4)
Using Predicated Execution to Improve the Performance of a Dynamically Scheduled Machine with Speculative Execution (1995) (4)
Identifying Obstacles In The Path To More (1997) (4)
Efficient Execution of Bursty Applications (2016) (4)
High Performance Prolog, The Multiplicative Effect of Several Levels of Implementation (1986) (3)
Experiments with HPS, a Restricted Data Flow Microarchitecture for High Performance Computers (1986) (3)
Branch Runahead: An Alternative to Branch Prediction for Impossible to Predict Branches (2021) (3)
SPAM: a microcode based tool for tracing operating system events (1987) (3)
Variable Length Path Branch (1998) (3)
Design and Implementation of A CMOS Chip for Prolog (1988) (3)
SEVERAL IMPLEMENTATIONS OF PROLOG, THE MICROARCHITECTURE PERSPECTIVE. (1986) (3)
The effect of speculative updating branch history on branch prediction accuracy, revisited (1994) (3)
The DSI and below: The architelcture/hardware component of a computer science curriculum (1988) (3)
Duplicon Cache: Mitigating Off-Chip Memory Bank and Bank Group Conflicts Via Data Duplication (2018) (3)
Workshop on Advancing Computer Architecture Research ( ACAR-1 ) Failure is not an Option : Popular Parallel Programming (2010) (3)
A Comparison Between the PLM and the MC 68020 as Prolog Processors (1988) (2)
Proceedings of the 5th international conference on High Performance Embedded Architectures and Compilers (2010) (2)
Proceedings of the 21st annual workshop on Microprogramming and microarchitecture (1988) (2)
A unifying theory of distributed processing (or, the Chutzpah one should expect when you invite a microarchitect into your sandbox) (2005) (2)
SPAM: a microcode based tool for tracing operating sytsem events (1988) (2)
Issues and problems in the I/O subsystem. I. The magnetic disk (1992) (2)
Minimum Search Tree Structures for Data Partitioned into Pages (1972) (2)
BranchNet : Using Offline Deep Learning To Predict Hard-To-Predict Branches (2019) (2)
Optimal andNear-Optimal Universal Logic Modules withInterconnected External Terminals (1973) (2)
Feedback Driven Pipelining (2010) (2)
Methodologies for experimental research in computer architecture and performance measurement (1990) (2)
Guest Editor's Introduction Real Machines: Design Choices/Engineering Trade-Offs (1989) (2)
HPSm2: A refined single-chip microengine (1988) (2)
Microcode and the protection of intellectual effort (1985) (2)
Track Piggybacking: An Improved Rebuild Algorithm for RAID5 Disk Arrays (1995) (2)
Components of a computer architecture education (1995) (2)
Retrofitting the VAX-11/780 Microarchitecture for IEEE Floating Point Arithmetic—Implementation Issues, Measurements, and Analysis (1985) (2)
Common Bonds: MIPS, HPS, Two-Level Branch Prediction, and Compressed Code RISC Processor (2016) (2)
Wrong Path Events : Exploiting Illegal and Unusual Program Behavior for Early Misprediction Recovery (2004) (1)
Microarchitecture choices (implementation of the VAX) (1989) (1)
Better than one operation per clock (panel): vectors, VLIW, and superscalar (1990) (1)
One BillionTransistors , One Uniprocessor (1)
High Performance Embedded Architectures and Compilers, 5th International Conference, HiPEAC 2010, Pisa, Italy, January 25-27, 2010. Proceedings (2010) (1)
Criticality Driven Fetch (2021) (1)
The Transformation Hierarchy in the Era of Multi-core (2007) (1)
Exploiting horizontal and vertical concurrency via the HPSm microprocessor (1987) (1)
Fast temporary storage for serial and parallel execution (1987) (1)
The microprocessor for scientific computing in the year 2000 (1996) (1)
Line Distillation: A Mechanism to Improve Cache Utilization (2006) (1)
Modifications to the VAX-11/780 microarchitecture to support IEEE floating point arithmetic (1983) (1)
Reducing critical path execution time by breaking critical loops (2005) (1)
Tailoring functional units and memory in a high performance Prolog architecture (1989) (1)
Staff Listing (2012) (1)
Proceedings of the 34th annual ACM/IEEE international symposium on Microarchitecture (2001) (1)
Tradeoffs in the design of a system for high level language interpretation (1983) (1)
Opening and keynote 1 (2004) (1)
Extending a Prolog architecture for high performance numeric computations (1989) (1)
Reducing Memory Access Latency via an Enhanced ( Compute Capable ) Memory Controller (2015) (1)
HPS, a new microachitecture: introduction and rationale (2000) (1)
Teaching and teaching computer architecture: two very different topics: (some opinions about each) (2003) (1)
Some results on the asymptotic behavior of functions on subsets of the natural numbers (1979) (1)
Exploiting horizontal and vertical concurrency via the HPSm microprocessor (1988) (1)
Single-threaded vs. multi-threaded (2007) (1)
Dynamic Merge Point Prediction (2020) (1)
Message from the Program Chairs (2018) (1)
Braids: out-of-order performance with almost in-order complexity (2007) (1)
Issues and Problems in the 1/0 Subsystem Part I - The Magnetic Disk (1992) (1)
A comparative performance evaluation of various state maintenance mechanisms (1993) (1)
Implementing a Prolog Machine with Multiple Functional Units (1988) (1)
Discussion on "AI & Scientific Computing: Are They Incompatible?" (1987) (0)
Toward the specification of an ISA for high performance computing engines. I. The hardware perspective (1992) (0)
The MPP Simulator - User's Manual. (1975) (0)
Keynote 1 - VLSI 2.0: R&D Post Moore (2013) (0)
AchievingOut-of-OrderPerformancewithAlmostIn-OrderComplexity (2008) (0)
Independent necessary conditions for functional completeness in m-valued logic (1977) (0)
Comparison of Aquarius and SPUR (Symbolic Processing upon RISC) Projects (1985) (0)
MICROPROCESSOR PERFORMANCE , PHASE 2 HARNESSING THE TRANSFORMATION HIERARCHY (2007) (0)
Micro-21 from the chair (1989) (0)
Researching Novel Systems: To Instantiate, Emulate, Simulate, or Analyticate? (2007) (0)
A Computing Course For All Freshmen Engineering Students (Half Architecture, Half Programming) (1997) (0)
Can They Be Fixed: Some Thoughts After 40 Years in the Business (2008) (0)
Computer Engineering (2020) (0)
The I/O Subsvstem (1994) (0)
2013-2014 Severo Ochoa : Research Seminar Lectures at BSC : book of abstracts (2014) (0)
HAWAII INTERNATIONAL CONFERENCE ON SYSTEM SCIENCES, 6TH, PROCEEDINGS, 1973. (2017) (0)
The microprocessor of the year 2014: do Pentium 4, Pentium M, and Power 5 provide any hints? (2005) (0)
Processor paradigms: evolution or disruption (2017) (0)
High-PerformaGce, High-Reliability Storage Subsystems (1994) (0)
Task Forces In Computer Architecture (1997) (0)
The High Performance Microprocessor in the Year 2013: What Will It Look Like? What It Won't Look Like? (2003) (0)
Yale Patt Recognized with Four Papers Among Inaugural Micro Test of Time Award (2017) (0)
The Effect of Instruction Fetch Bandwidth on Value Prediction (1998) (0)
Greater performance and better efficiency: Predicated execution has shown us the way (2016) (0)
The future of simulation: A field of dreams (2004) (0)
Education in computer engineering (2003) (0)
HPS papers: A retrospective (2016) (0)
Foreword (2006) (0)
Compiler-Assisted Dynamic Predicated Execution of Complex Control-Flow Structures (2006) (0)
Microprocessors for the years 2001 and 2008: Where will we be in 2001? What will still need to be done for 2008? (1999) (0)
IISWC 2009 reviewers (2009) (0)
The Challenges of Multicore: Information and Mis-Information (2009) (0)
Machine learning and quantum computing; is there anything else worth working on? (2018) (0)
Components of a computer architecture education: optimal and suboptimal (1995) (0)
HPS Microarchitecture (2011) (0)
Real Machines Design Choices / Engineering Trade-Offs (2001) (0)
7-1-1992 Report of the Purdue Workshop on Grand Challenges in Computer Architecture ! for the Support of High Performance Computing (2013) (0)
Highest performance computing machines (1992) (0)
External review of the Naval Postgraduate School by visiting civilian professionals, 1993-1994 edition. (1994) (0)
ImprovingGPUPerformanceviaLargeWarps an dTwo-LevelWarpScheduling (2011) (0)
Wish Branch : A New Control Flow Instruction Combining Conditional Branching and Predicated Execution (2005) (0)
Multi-core demands multi-interfaces (2009) (0)
High performance supercomputers: should the individual processor be more than a brick? (2012) (0)
Keynote speaker (2022) (0)
Software technology track . Computer architecture task forces (1997) (0)
Computer Architecture Research and Future Microprocessors: Where Do We Go from Here? (2006) (0)
What Else Is Broken? Can We Fix It? (2009) (0)
Scanning the Issue - Special Issue on Microprocessors (1995) (0)
Investigation of Microprogrammable Microprocessors. (1977) (0)
Introduction to computing - the correct (bottom-up) approach (1997) (0)
First courses and fundamentals (1996) (0)
Real Machines: Design Choices / Engineering Trade-Offs - Guest Editor's Introduction (1989) (0)
Message from the General Chair (2018) (0)
ImprovingGPUPerformanceviaLargeWarps andTwo-LevelWarpScheduling (2011) (0)
Higher and higher performance microprocessors: are the problems just too hard to solve? (2000) (0)
COMPARISON OF SEVERAL EVOLVING (UNIVERSITY) SUPERCOMPUTER ARCHITECTURES. (1984) (0)
The microprocessor of 2020: Why you should care, and what you can do about it (2010) (0)
Computer architecture education: mechanical engineers need it too (1999) (0)

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Published Works

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What Schools Are Affiliated With Yale Patt?

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Yale Patt's AcademicInfluence.com Rankings