Yervant Zorian

Yervant Zorian's AcademicInfluence.com Rankings

Yervant Zorian

Engineering

#6972

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#8329

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Electrical Engineering

#2135

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#2240

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engineering Degrees

Yervant Zorian

Computer Science

#9319

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#9792

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Computer Architecture

#58

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#60

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Database

#6289

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#6521

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computer-science Degrees

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Engineering
Computer Science

Yervant Zorian's Degrees

PhD Electrical Engineering University of Southern California
Masters Electrical Engineering University of Southern California

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Yervant Zorian's Published Works

Number of citations in a given year to any of this author's works

Total number of citations to an author for the works they published in a given year. This highlights publication of the most important work(s) by the author

Published Works

TRANSACTIONS ON KNOWLEDGE AND DATA ENGINEERING (2005) (655)
Testing embedded-core based system chips (1998) (608)
A distributed BIST control scheme for complex VLSI devices (1993) (603)
Testing 3D chips containing through-silicon vias (2009) (320)
On-Line Testing for VLSI—A Compendium of Approaches (1998) (250)
Wrapper design for embedded core test (2000) (240)
Introducing Core-Based System Design (1997) (225)
2001 Technology Roadmap for Semiconductors (2002) (223)
Built in self repair for embedded high density SRAM (1998) (211)
Embedded-memory test and repair: infrastructure IP for SoC yield (2003) (187)
Testing the Interconnect of RAM-Based FPGAs (1998) (166)
Towards a standard for embedded core test: an example (1999) (156)
On IEEE P1500's Standard for Embedded Core Test (2002) (142)
Test requirements for embedded core-based systems and IEEE P1500 (1997) (140)
Test of RAM-based FPGA: methodology and application to the interconnect (1997) (117)
Principles of testing electronic systems (2000) (112)
Challenges in embedded memory design and test (2005) (91)
2003 technology roadmap for semiconductors (2004) (85)
On using IEEE P1500 SECT for test plug-n-play (2000) (81)
Testing the monster chip (1999) (80)
Test of future system-on-chips (2000) (74)
Overview of the IEEE P1500 standard (2003) (72)
Challenges in testing core-based system ICs (1999) (72)
A structured testability approach for multi-chip modules based on BIST and boundary-scan (1994) (67)
Low power/energy BIST scheme for datapaths (2000) (66)
Guest Editor's Introduction: What is Infrastructure IP? (2002) (63)
SoC yield optimization via an embedded-memory test and repair infrastructure (2004) (61)
Built-in self-test for digital integrated circuits (1994) (59)
Instruction-Based Self-Testing of Processor Cores (2002) (57)
An Effective BIST Scheme for ROM's (1992) (56)
Easily Testable Cellular Carry Lookahead Adders (2003) (56)
Deterministic software-based self-testing of embedded processor cores (2001) (56)
Switching activity generation with automated BIST synthesis forperformance testing of interconnects (2001) (55)
Embedded memory test and repair: infrastructure IP for SOC yield (2002) (54)
Guest Editors' Introduction: Design for Yield and Reliability (2004) (54)
Effective software self-test methodology for processor cores (2002) (54)
Embedded Memory Test & Repair : Infrastructure IP for SOC Yield Yervant Zorian Virage Logic (2002) (53)
Minimal March tests for unlinked static faults in random access memories (2005) (53)
PSBIST: A partial-scan based built-in self-test scheme (1993) (52)
Different experiments in test generation for XILINX FPGAs (2000) (50)
An Effective Built-In Self-Test Scheme for Parallel Multipliers (1999) (49)
IS-FPGA : a new symmetric FPGA architecture with implicit scan (2001) (48)
SRAM-based FPGA's: testing the LUT/RAM modules (1998) (47)
Test pattern and test configuration generation methodology for the logic of RAM-based FPGA (1997) (39)
Minimizing the number of test configurations for different FPGA families (1999) (39)
RAM-based FPGAs: a test approach for the configurable logic (1998) (38)
Low-cost software-based self-testing of RISC processor cores (2003) (38)
HD/sup 2/BIST: a hierarchical framework for BIST scheduling, data patterns delivering and diagnosis in SoCs (2000) (38)
SRAM-Based FPGAs: Testing the Embedded RAM Modules (1999) (38)
System chip test: how will it impact your design? (2000) (37)
Programmable BIST Space Compactors (1996) (37)
Application and analysis of rt-level software-based self-testing for embedded processor cores (2003) (37)
An approach for evaluation of redundancy analysis algorithms (2001) (36)
TRANSACTIONS ON SOFTWARE ENGINEERING (2004) (36)
IEEE Std 1500 Enables Modular SoC Testing (2009) (35)
Embedded Processor-Based Self-Test (2004) (34)
An effective BIST scheme for datapaths (1996) (33)
A Robust Solution for Embedded Memory Test and Repair (2011) (33)
Optimizing error masking in BIST by output data modification (1990) (32)
Novel technique for testing FPGAs (1998) (32)
Fault modeling and test algorithm creation strategy for FinFET-based memories (2014) (32)
System-chip test strategies (1998) (31)
Programmable space compaction for BIST (1993) (31)
A universal testability strategy for multi-chip modules based on BIST and boundary-scan (1992) (31)
Integration of partial scan and built-in self-test (1995) (29)
Embedded memory reliability: the SER challenge (2004) (28)
An effective BIST scheme for ring-address type FIFOs (1994) (28)
IoT: Source of test challenges (2016) (28)
On the generation of pseudo-deterministic two-patterns test sequence with LFSRs (1997) (27)
Effective Built-In Self-Test for Booth Multipliers (1998) (26)
Sequential Fault Modeling and Test Pattern Generation for CMOS Iterative Logic Arrays (2000) (25)
EEODM: An effective BIST scheme for ROMs (1990) (24)
Challenges and Options (1998) (24)
Embedding infrastructure IP for SOC yield improvement (2002) (23)
An effective BIST architecture for fast multiplier cores (1999) (23)
Minimal march test algorithm for detection of linked static faults in random access memories (2006) (22)
Analyzing the test generation problem for an application-oriented test of FPGAs (2000) (22)
TRANSACTIONS ON PARALLEL AND DISTRIBUTED SYSTEMS (2005) (22)
IEEE Standard 1500 Compliance Verification for Embedded Cores (2008) (22)
An effective BIST scheme for carry-save and carry-propagate array multipliers (1995) (21)
Advanced ECC solution for automotive SoCs (2017) (21)
An effective BIST scheme for Booth multipliers (1995) (21)
Functional tests for arbitration SRAM-type FIFOs (1992) (21)
A methodology for design and evaluation of redundancy allocation algorithms (2004) (20)
A New Method for March Test Algorithm Generation and Its Application for Fault Detection in RAMs (2012) (20)
A structured approach to macrocell testing using built-in self-test (1990) (20)
Defect injection, Fault Modeling and Test Algorithm Generation Methodology for STT-MRAM (2018) (20)
Test and Repair Methodology for FinFET-Based Memories (2015) (19)
Testing the configurable interconnect/logic interface of SRAM-based FPGA's (1999) (18)
Minimal March Tests for Detection of Dynamic Faults in Random Access Memories (2007) (18)
IEEE 1500 utilization in SOC design and test (2005) (18)
Automated BIST for regular structures embedded in ASIC devices (1990) (18)
TOF: a tool for test pattern generation optimization of an FPGA application oriented test (2000) (17)
Impact of soft error challenge on SoC design (2005) (16)
Minimal March Tests for Dynamic Faults in Random Access Memories (2006) (16)
Guest Editor's Introduction: Advances in Infrastructure IP (2003) (16)
A March-based fault location algorithm for static random access memories (2002) (16)
An effective BIST scheme for arithmetic logic units (1997) (15)
Power Dissipation During Testing: Should We Worry About it? (1997) (15)
Generic BIST architecture for testing of content addressable memories (2011) (14)
The Best Influences on Software Engineering (1999) (14)
A hierarchical infrastructure for SoC test management (2003) (13)
Functional test for shifting-type FIFOs (1995) (13)
A March-based fault location algorithm for static random access memories (2002) (13)
Effective march algorithms for testing single-order addressed memories (1993) (13)
An effective functional safety solution for automotive systems-on-chip (2017) (13)
Design and Test of Core-Based Systems on Chips (1997) (12)
HD-BIST: a hierarchical framework for BIST scheduling and diagnosis in SOCs (1999) (12)
Testing the Local Interconnect Resources of SRAM-Based FPGA's (2000) (12)
Optimizing manufacturability by design for yield (2004) (12)
Higher Certainty of Error Coverage by Output Data Modification (1984) (12)
Design for test and reliability in ultimate CMOS (2012) (12)
Count-based BIST compaction schemes and aliasing probability computation (1992) (11)
Power-/Energy Efficient BIST Schemes for Processor Data Paths (2000) (11)
Scaling deeper to submicron: on-line testing to the rescue (1999) (11)
Built-in self-test (1999) (11)
Designing self-testable multi-chip modules (1996) (11)
Symmetry Measure for Memory Test and Its Application in BIST Optimization (2011) (11)
A D&T Roundtable: Online Test (1999) (11)
Emerging trends in VLSI test and diagnosis (2000) (10)
Test configuration minimization for the logic cells of SRAM-based FPGAs: a case study (1999) (10)
Memory Physical Aware Multi-Level Fault Diagnosis Flow (2018) (10)
Experimental study on Hamming and Hsiao codes in the context of embedded applications (2017) (10)
Efficient Totally Self-Checking Shifter Design (1998) (10)
Preliminary Outline of the IEEE PI 500 Scalable Architecture for Testing Embedded Cores (1999) (10)
Fault-secure shifter design: results and implementations (1997) (10)
Guest Editors' Introduction: The Status of IEEE Std 1500 (2009) (10)
Selecting programmable space compactors for BIST using genetic algorithms (1994) (10)
SRAM-based FPGA's: testing the interconnect/logic interface (1998) (10)
Test solutions for nanoscale Systems-on-Chip: Algorithms, methods and test infrastructure (2013) (9)
An effective solution for building memory BIST infrastructure based on fault periodicity (2013) (9)
Fault models and tests for Ring Address Type FIFOs (1994) (9)
Extending fault periodicity table for testing faults in memories under 20nm (2014) (9)
A distributed BIST technique for diagnosis of MCM interconnections (1998) (9)
Impact of process variations on read failures in SRAMs (2013) (8)
An effective functional safety infrastructure for system-on-chips (2017) (8)
An Effective Multi-Chip BIST Scheme (1997) (8)
Multi-chip module test strategies (1997) (8)
Minimal March-Based Fault Location Algorithm with Partial Diagnosis for All Static Faults in Random Access Memories (2006) (8)
Today's SOC test challenges (2005) (8)
On testing of non-isolated embedded legacy cores and their surround logic (1999) (8)
Fundamentals of MCM Testing and Design-for-Testability (1997) (8)
An Approach to Minimize the Test Configuration for the Logic Cells of the Xilinx XC4000 FPGAs Family (2000) (7)
Nanoscale Design & Test Challenges (2005) (7)
High-level design validation and test (1998) (7)
’ Introduction : Design for Yield and Reliability (6)
An Efficient March-Based Three-Phase Fault Location and Full Diagnosis Algorithm for Realistic Two-Operation Dynamic Faults in Random Access Memories (2008) (6)
Built-in self-test with an alternating output (1998) (6)
Testing Embedded Cores (1997) (6)
Fault models and tests specific for FIFO functionality (1993) (6)
Integrating embedded test infrastructure in SRAM cores to detect aging (2013) (6)
Multi-chip module technology (1995) (6)
An Effective Deterministic BIST Scheme for Shifter/Accumulator Pairs in Datapaths (2001) (6)
Impact of parameter variations on FinFET faults (2015) (6)
A High-Level EDA Environment for the Automatic Insertion of HD-BIST Structures (1999) (6)
Modeling and Testing of Aging Faults in FinFET Memories for Automotive Applications (2018) (5)
Reducing embedded SRAM test time under redundancy constraints (2004) (5)
Advanced Uniformed Test Approach For Automotive SoCs (2018) (5)
Securing test infrastructure of system-on-chips (2016) (5)
An effective embedded test & diagnosis solution for external memories (2015) (5)
Overview study on fault modeling and test methodology development for FinFET-based memories (2015) (5)
An effective BIST architecture for sequential fault testing in array multipliers (1999) (5)
DFM—Don't care or competitive weapon? (2009) (5)
Boundary Scan-Based Relay Wave Propagation Test of Arrays of Identical Structures (2001) (5)
Keynote 3: "Ensuring robustness in today's IoT era" (2015) (5)
Robust and low-cost BIST architectures for sequential fault testing in datapath multipliers (2001) (5)
Computing the error escape probability in count-based compaction schemes (1990) (5)
A method for delay fault self-testing of macrocells (1993) (4)
Guest Editorial: Special Issue on Testing of 3D Stacked Integrated Circuits (2012) (4)
An efficient testing methodology for embedded flash memories (2017) (4)
Fault Awareness for Memory BIST Architecture Shaped by Multidimensional Prediction Mechanism (2019) (4)
Testing semiconductor chips: trends and solutions (1999) (4)
Yield improvement and repair trade-off for large embedded memories (2000) (4)
Some experiments in test pattern generation for FPGA-implemented combinational circuits (2000) (4)
A D&T Roundtable: Testing Mixed Logic and DRAM Chips (1998) (4)
Leveraging infrastructure IP for SoC yield (2003) (3)
Infrastructure IP for SOC (2004) (3)
Designing fault-tolerant, testable, VLSI processors using the IEEE P1149.1 boundary-scan architecture (1989) (3)
Advanced functional safety mechanisms for embedded memories and IPs in automotive SoCs (2017) (3)
Synthesis of BIST hardware for performance testing of MCM interconnections (1998) (3)
SRAM-Based FPGAs: A Fault Model for the Configurable Logig Modules (1998) (3)
Accounting for chip yield at the application level: A case study of a H. 264 video application (2006) (3)
IEEE recommended practice for powering and grounding electronic equipment. (Color Book Series - Emerald Book) (1999) (3)
Error-Free Products (2001) (3)
Testing the unidimensional interconnect architecture of symmetrical SRAM-based FPGA (2002) (2)
Area versus detection latency trade-offs in self-checking memory design (1995) (2)
The future of fault tolerant computing (2015) (2)
D&T Expands (1999) (2)
SRAM retention testing: zero incremental time integration with March algorithms (2005) (2)
A Discussion on Test Pattern Generation for FPGA—Implemented Circuits (2001) (2)
DFM Drives Changes in Design Flow (2005) (2)
Optimal multiple chain relay testing scheme for MCMs on large area substrates (1996) (2)
Relay propagation scheme for testing of MCMs on large area substrates (1996) (2)
Test and reliability concerns for 3D-ICs (2010) (2)
Proceedings of the 2002 IEEE International Workshop on Memory Technology, Design and Testing : (MTDT 2002) : 10-12 July, 2002, Isle of Bendor, France (2002) (2)
Multi-chip modules testing and DFT (1995) (2)
A power based memory BIST grouping methodology (2015) (2)
Do you practice safe test? What we found out about your habits (1994) (2)
Guest Editors' Introduction: Big Innovations in Small Packages (2006) (2)
Special Session 13A: Panel : Mitigating Reliability, Yield and Power Issues in Nano-CMOS: Design Problem or EDA Problem? (2008) (1)
A test interface for built-in test of non-isolated scanned cores (2003) (1)
Cover Feature Testing Embedded-Core-Based System Chips (1)
Innovative Practices on In-System Test and Reliability of Memories (2019) (1)
Guest Editors' Introduction: Design & Test of a High-Volume 3-D Stacked Graphics Processor With High-Bandwidth Memory (2017) (1)
An efficient March test for detection of all two-operation dynamic faults from subclass Sav (2010) (1)
Fault isolation for nonisolated blocks (2004) (1)
Compliance Verification for Embedded Cores (1)
A March-Based Fault Location Algorithm with Partial and Full Diagnosis for All Simple Static Faults in Random Access Memories (2007) (1)
BIST for ring-address SRAM-type FIFOs (1994) (1)
Functional tests for ring-address SRAM-type FIFOs (1994) (1)
System-Chip Test Strategies (Tutorial). (1998) (1)
Flexibility and Programmability (2000) (1)
Huge Storage Capacity (2001) (1)
Robustly testable array multipliers under realistic sequential cell fault model (1998) (1)
Low‐Power Testing for Low‐Power LSI Circuits (2012) (1)
Application of defect injection flow for fault validation in memories (2013) (1)
Effective low power BIST for datapaths (poster paper) (2000) (1)
Advanced ECC-Based FIT Rate Mitigation Technique for Automotive SoCs (2018) (1)
Test and Diagnosis Solution for Functional Safety (2020) (1)
Distributed Diagnosis of Interconnections in SoC and MCM Designs (2004) (1)
The 10th China Test Conference (2018) (1)
Next Generation Test, Diagnostics and Yield Challenges for EDA, ATE, IP and Fab - A Perspective from All Sides (2007) (0)
An approach for designing total-dose tolerant MCMs based on current monitoring (1995) (0)
Tributes to Prof. Edward J. McCluskey (2008) (0)
Collaboration and Technology: 21st International Conference, CRIWG 2015, Yerevan, Armenia, September 22-25, 2015, Proceedings (2015) (0)
Semiconductor Industry Disaggregation vs Reaggregation: Who Will be the Shark? (2005) (0)
Session Abstract (2006) (0)
Keynotes: Robustness challenges in the internet of things (2017) (0)
Session details: Advanced test solutions (2004) (0)
East Meets West [Guest Editors' Introduction:] (1996) (0)
Investment vs. yield relationship for memories in SOC (2004) (0)
Integration Continues (1999) (0)
Comité du programme technique / Technical Program Committee (2006) (0)
Guest Editors' Introduction: Highlights of the 50th DAC (2014) (0)
Design & Test in the new decade: Continuity and new directions (2010) (0)
IEEE Computer Society TTTC: Test Technology Technical Council (2005) (0)
Innovative Practices Track: What’s Next for Automotive: Where and How to Improve Field Test and Enhance SoC Safety (2022) (0)
Session Abstract (2006) (0)
Case Studies — Experimental Results (2004) (0)
Conference reports (1996) (0)
Session 2 A : Design Methods for High Performance Applications (2015) (0)
Built-in quality assurance (1994) (0)
Memory FIT Rate Mitigation Technique for Automotive SoCs (2019) (0)
Guest Editors' Introduction: The Status of IEEE Std 1500 - Part 2 (2009) (0)
Panel Session - Vertical integration versus disaggregation (2009) (0)
Proceedings, IDT 2007 : the 2007 2nd International Design and Test Workshop (2007) (0)
Testing of Processor-Based SoC (2004) (0)
EIC Message (2020) (0)
Embedded tutorial: TRP: integrating embedded test and ATE (2001) (0)
Welcome to the IDT 2016 (2016) (0)
Tutorial I: Topic: Automotive test strategies (2017) (0)
A Novel Protection Technique for Embedded Memories with Optimized PPA (2022) (0)
Session details: Test cost reduction for SOCS (2002) (0)
IC design in 65 nm and beyond: evolution or revolution? [Sunday Panel] (2004) (0)
Once Again, a Super Issue (1998) (0)
Proceedings, 2001 IEEE International Workshop on Memory Technology, Design and Testing, August 6-7, 2001, San Jose, California, USA (2001) (0)
Making Manufacturing Work For You (2007) (0)
Vertical integration versus disaggregation (2009) (0)
IEEE CASS becomes D&T Copublisher (2003) (0)
IP session on ISO26262 EDA (2018) (0)
Session details: Making manufacturing work for you (2007) (0)
17th IEEE East-West Design and Test Symposium (2019) (0)
Decision-Making for Complex SoCs in Consumer Electronic Products (2006) (0)
Conference Reports (2003) (0)
Session Abstract (2006) (0)
The Back Story: He Delivers (2005) (0)
Design of Processor-Based SoC (2004) (0)
System-on-Chip: Embedded Test Strategies (2001) (0)
A Cross-layer approach to hardware error mitigation : A Case Study of a JPEG 2000 Imaging Application (2006) (0)
Banquet speaker (2015) (0)
Software-Based Processor Self-Testing (2004) (0)
Guest Editors' Introduction: East Meets West (1996) (0)
Embedded in this issue (2000) (0)
How to determine the necessity for emerging solutions (2005) (0)
Guest Editor's Introduction: Examples of Management Decision Criteria (2009) (0)
On-chip cores take on yield problems (2003) (0)
Fault isolation using tests for non-isolated blocks (2002) (0)
Design, test & repair methodology for FinFET-based memories (2014) (0)
T1: Design for Manufacturability (2005) (0)
Special session 12C: Town-hall meeting “young professionals in test” (2013) (0)
Session details: Novel approaches in test coast reduction (2003) (0)
Optimal Processing Resources (2001) (0)
Focus on DRAMs (1999) (0)
Preface (2001) (0)
SoC Testing and P1500 Standard (2000) (0)
Tutorial Statement (2000) (0)
Special session 12C: Young professionals in test — Town meeting (2014) (0)
Organizing committee (2015) (0)
Optimizing SoC manufacturability (2005) (0)
The effective use of BIST and boundary-scan in multi-chip module testing (1994) (0)
An efficient approach for memory repair by reducing the number of spares (2015) (0)
Fault and Test Algorithm Periodicity Hypothesis in MemoryDevices and Its Application to Memory BIST ProcessorArchitecture (2012) (0)
Guest Editorial: Special Issue on Testing of 3D Stacked Integrated Circuits (2012) (0)
D&T: 15th Year in Service (1998) (0)
12th "IEEE Latin-American Test Workshop" Porto de Galinhas, Brazil, 27-30 March 2011 (2011) (0)
Processor Testing Techniques (2004) (0)
Management Day Session 150 - How to determine the necessity for emerging solutions (2005) (0)
IEEE Circuits and Systems Society 2005 VLSI Transactions Best Paper Award (2005) (0)
Automated flow for test pattern creation for IPs in SoC (2017) (0)
Embedded-Quality for Test (2000) (0)
An efficient fault diagnosis and localization algorithm for Successive-Approximation Analog to Digital Converters (2013) (0)
Guest Editors' Introduction: DFM Drives Changes in Design Flow (2005) (0)
ITC 97 Panel Sessions (1998) (0)
Processor-Based Testing of SoC (2004) (0)
ETS 2011 STEERING AND PROGRAM COMMITTEES (2011) (0)
Trends & Challenges in Today's Automotive SOCs (2019) (0)
Choosing flows and methodologies for SoC design (2005) (0)
Organizing and Program Committee (1996) (0)
A Wrapper Serial Output ( WSO ) terminal • A Wrapper clock ( WRCK ) terminal • A Wrapper Reset ( WRSTN ) terminal (2002) (0)
Detection & diagnostics in today's advanced technology nodes (2014) (0)
Keynote address 2: “Advances in boolean satisfiability and its application in EDA” (2008) (0)
Design practices for better reliability and yield (tutorial) (2000) (0)
FIT Rate Calculation and Mitigation Techniques for Advanced Technologies and Automotive Applications (2018) (0)
Keynote Address 2 (2008) (0)
Message From the Steering Committee (2020) (0)
Session Abstract (2007) (0)
Tutorials A1 Built-in Self-test for System-chips and beyond B1 Reuse of Virtual Components in System-on-chip Environments C1 System-level Power Optimisation: Techniques and Tools (0)
Session details: Session 7A: Manufacturing test: stuck-at to crosstalk (2001) (0)
Panel: Regional and global collaboration models to boost chip design sector in the middle east (2013) (0)
Addressing Test Challenges in Advanced Technology Nodes (2012) (0)
Tutorial 3 High-level Design Validation And Test (1998) (0)
Special Session 9B: Embedded Tutorial: Nanoelectronics - What Next? From Moore's Law to Feynman's Vision (2008) (0)
Yield threats and inadequacy of one-time test (2003) (0)
Guest Editorial (1997) (0)
Chip Cooling: Why – How (2004) (0)
Wednesday Afternoon Pleanry Talk Title: Optimizing SoC Manufacturability (2005) (0)
On-Line Testing for Secure Implementations: Design and Validation (2005) (0)
Panel Summaries (1996) (0)
Guest Editor's Introduction (2018) (0)
Wider Coverage (2000) (0)
Message from the LATS2015 Chairs (2015) (0)
Automotive Test and Reliability (2021) (0)
Design & Test Education in Asia (2004) (0)
Systems On Silicon: Design and Test Challenges (1997) (0)
In-field test solution for enhancing safety in automotive applications (2022) (0)
Embedded Core-based System-on-Chip Test Strategies (2006) (0)
Tradeoffs and Choices for Emerging SoCs in High-End Applications (2006) (0)
International Test Conference in Asia (ITC-Asia) - Bridging ITC and Test Community in Asia (2019) (0)

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Yervant Zorian's Academic­Influence.com Rankings

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Published Works

Yervant Zorian's AcademicInfluence.com Rankings