Yuan Taur

Yuan Taur's AcademicInfluence.com Rankings

Yuan Taur

Engineering

#6636

World Rank

#7972

Historical Rank

Electrical Engineering

#2004

World Rank

#2107

Historical Rank

engineering Degrees

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Engineering

Yuan Taur's Degrees

PhD Electrical Engineering Stanford University
Masters Electrical Engineering Stanford University
Bachelors Electrical Engineering National Taiwan University

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Yuan Taur's Published Works

Number of citations in a given year to any of this author's works

Total number of citations to an author for the works they published in a given year. This highlights publication of the most important work(s) by the author

Published Works

Fundamentals of Modern VLSI Devices (1998) (1994)
Device scaling limits of Si MOSFETs and their application dependencies (2001) (1416)
CMOS scaling into the nanometer regime (1997) (875)
Quantum-mechanical modeling of electron tunneling current from the inversion layer of ultra-thin-oxide nMOSFET's (1997) (795)
CMOS design near the limit of scaling (2002) (378)
Analytic solutions of charge and capacitance in symmetric and asymmetric double-gate MOSFETs (2001) (360)
Generalized scale length for two-dimensional effects in MOSFETs (1998) (309)
A continuous, analytic drain-current model for DG MOSFETs (2004) (300)
Self-aligned (top and bottom) double-gate MOSFET with a 25 nm thick silicon channel (1997) (259)
An analytical solution to a double-gate MOSFET with undoped body (2000) (253)
25 nm CMOS design considerations (1998) (251)
Three-dimensional "atomistic" simulation of discrete random dopant distribution effects in sub-0.1 /spl mu/m MOSFET's (1993) (224)
A new 'shift and ratio' method for MOSFET channel-length extraction (1992) (215)
Modeling and characterization of quantization, polysilicon depletion, and direct tunneling effects in MOSFETs with ultrathin oxides (1999) (194)
Simulation of Nanoscale Multidimensional Transient Heat Conduction Problems Using Ballistic-Diffusive Equations and Phonon Boltzmann Equation (2005) (152)
A 2-D analytical solution for SCEs in DG MOSFETs (2004) (149)
Explicit Continuous Models for Double-Gate and Surrounding-Gate MOSFETs (2007) (141)
Scaling of Nanowire Transistors (2008) (139)
CMOS scaling into the 21st century: 0.1 µm and beyond (1995) (125)
An analytic potential model for symmetric and asymmetric DG MOSFETs (2006) (125)
Design of Tunneling Field-Effect Transistors Based on Staggered Heterojunctions for Ultralow-Power Applications (2010) (122)
Review and Critique of Analytic Models of MOSFET Short-Channel Effects in Subthreshold (2012) (116)
A Distributed Bulk-Oxide Trap Model for $\hbox{Al}_{2} \hbox{O}_{3}$ InGaAs MOS Devices (2012) (114)
Monte Carlo modeling of threshold variation due to dopant fluctuations (1999) (114)
MOSFET channel length: extraction and interpretation (2000) (101)
Monte Carlo modeling of threshold variation due to dopant fluctuations (1999) (88)
$\hbox{In}_{0.53}\hbox{Ga}_{0.47}\hbox{As}$ Channel MOSFETs With Self-Aligned InAs Source/Drain Formed by MEE Regrowth (2009) (87)
Analytic Charge Model for Surrounding-Gate MOSFETs (2007) (87)
A high-performance 0.25- mu m CMOS technology. II. Technology (1992) (87)
Discrete random dopant distribution effects in nanometer-scale MOSFETs (1998) (83)
Comprehensive Analysis of Short-Channel Effects in Ultrathin SOI MOSFETs (2013) (79)
A high-performance 0.25- mu m CMOS technology. I. Design and characterization (1992) (75)
The incredible shrinking transistor (1999) (73)
A Review on Compact Modeling of Multiple-Gate MOSFETs (2009) (72)
Short-Channel Effects in Tunnel FETs (2015) (72)
A Unified Analytic Drain–Current Model for Multiple-Gate MOSFETs (2008) (66)
Scaling MOSFETs to 10 nm: Coulomb effects, source starvation, and virtual source model (2009) (64)
A variable-size shallow trench isolation (STL) technology with diffused sidewall doping for submicron CMOS (1988) (63)
Design and performance considerations for sub-0.1 /spl mu/m double-gate SOI MOSFET'S (1994) (61)
Interface-State Modeling of $\hbox{Al}_{2}\hbox{O}_{3}$ –InGaAs MOS From Depletion to Inversion (2012) (57)
A new planarization technique, using a combination of RIE and chemical mechanical polish (CMP) (1989) (56)
Conversion gain in a Josephson effect mixer (1974) (54)
Modeling and Design of Ferroelectric MOSFETs (2011) (51)
Experimental high performance sub-0.1 /spl mu/m channel nMOSFET's (1994) (51)
Analysis of Source Doping Effect in Tunnel FETs With Staggered Bandgap (2015) (50)
Channel profile optimization and device design for low-power high-performance dynamic-threshold MOSFET (1996) (49)
A 23.8-GHz SOI CMOS tuned amplifier (2002) (48)
A Two-Dimensional Analytical Solution for Short-Channel Effects in Nanowire MOSFETs (2009) (47)
Design considerations for CMOS near the limits of scaling (2002) (47)
A novel high-performance lateral bipolar on SOI (1991) (46)
An Analytic Model for Heterojunction Tunnel FETs With Exponential Barrier (2015) (45)
Experimental evaluation of carrier transport and device design for planar symmetric/asymmetric double-gate/ground-plane CMOSFETs (2001) (45)
Effect of body doping on double-gate MOSFET characteristics (2007) (44)
Reduction of TFET OFF-Current and Subthreshold Swing by Lightly Doped Drain (2016) (43)
Analysis of Short-Channel Effects in Junctionless DG MOSFETs (2017) (42)
A Short-Channel $I$ – $V$ Model for 2-D MOSFETs (2016) (42)
On–Off Charge–Voltage Characteristics and Dopant Number Fluctuation Effects in Junctionless Double-Gate MOSFETs (2012) (41)
Diameter-independent hole mobility in Ge/Si core/shell nanowire field effect transistors. (2014) (40)
Doping of n+ and p+ polysilicon in a dual-gate CMOS process (1988) (40)
On the scaling limit of ultrathin SOI MOSFETs (2006) (39)
A Distributed Model for Border Traps in MOS Devices (2011) (39)
Parametric amplification and oscillation at 36 GHz using a point contact Josephson junction. Technical report 1 Feb 1976--31 Jan 1977 (1976) (38)
Defect generation in 3.5 nm silicon dioxide films (1994) (36)
Conversion gain and noise in a Josephson mixer. Technical report (1973) (36)
A Distributed Model for Border Traps in $\hbox{Al}_{2} \hbox{O}_{3}-\hbox{InGaAs}$ MOS Devices (2011) (35)
Study of boron penetration through thin oxide with p+-polysilicon gate (1989) (35)
A review of the Z 2 -FET 1T-DRAM memory: Operation mechanisms and key parameters (2017) (32)
A half-micron CMOS logic generation (1995) (31)
Fabrication of CMOS on ultrathin SOI obtained by epitaxial lateral overgrowth and chemical-mechanical polishing (1990) (31)
A 26.5 GHz silicon MOSFET 2:1 dynamic frequency divider (2000) (31)
Low-noise Josephson mixers at 115 GHz using recyclable point contacts (1978) (30)
An analytic model for threshold voltage shift due to quantum confinement in surrounding gate MOSFETs with anisotropic effective mass (2009) (30)
Josephson Junctions as Heterodyne Detectors (1974) (29)
Relaxation Oscillations in Point Contact Josephson Junctions. (1975) (27)
Noise in Josephson point contacts with and without rf bias (1974) (27)
Modeling and Characterization of n+- and p+-Polysilicon-Gated Ultra Thin Oxides (21-26 A) (1997) (26)
Determination of energy and spatial distribution of oxide border traps in In0.53Ga0.47As MOS capacitors from capacitance-voltage characteristics measured at various temperatures (2014) (25)
A unified charge model for symmetric double-gate and surrounding-gate MOSFETs (2008) (24)
Effects of oxide thickness and temperature on dispersions in InGaAs MOS C-V characteristics (2014) (24)
Josephson-junction mixer analysis using frequency-conversion and noise-correlation matrices (1980) (24)
A Laser-Induced Traveling-Wave Device for Generating Millimeter Waves (1981) (24)
High-performance 0.07-μm CMOS with 9.5-ps gate delay and 150 GHz f/sub T/ (1997) (23)
DC and AC performance analysis of 25 nm symmetric/asymmetric double-gate, back-gate and bulk CMOS (2000) (23)
Self-consistent 1-D Schrödinger–Poisson solver for III–V heterostructures accounting for conduction band non-parabolicity (2010) (23)
Characterization and modeling of a latchup-free 1-µm CMOS technology (1984) (23)
Effect of Gate Overlap and Source/Drain Doping Gradient on 10-nm CMOS Performance (2006) (22)
CMOS circuit technology for sub-ambient temperature operation (2000) (22)
The influence of source and drain junction depth on the short-channel effect in MOSFETs (2005) (20)
An ultra-low power 0.1 /spl mu/m CMOS (1994) (20)
Saturation transconductance of deep-submicron-channel MOSFETs (1993) (20)
Ultralow Defect Density at Sub-0.5 nm HfO2/SiGe Interfaces via Selective Oxygen Scavenging. (2018) (20)
Modeling of Short-Channel Effects in DG MOSFETs: Green’s Function Method Versus Scale Length Model (2018) (19)
4- and 13-GHz tuned amplifiers implemented in a 0.1-μm CMOS technology on SOI, SOS, and bulk substrates (1998) (19)
A comprehensive model on field-effect pnpn devices (Z 2 -FET) (2017) (19)
Comparison of Bulk-Oxide Trap Models: Lumped Versus Distributed Circuit (2013) (19)
A comprehensive study of hot-carrier instability in p- and n-type poly-Si gated MOSFET's (1994) (18)
Compact modeling of quantum effects in symmetric double-gate MOSFETs (2010) (18)
Full-swing complementary BiCMOS logic circuits (1989) (18)
Gate-Length-Dependent Strain Effect in n- and p-Channel FinFETs (2009) (17)
Dimensionality Dependence of TFET Performance Down to 0.1 V Supply Voltage (2016) (17)
RF perspective of sub-tenth-micron CMOS (1998) (17)
Sidewall oxidation of polycrystalline-silicon gate (1989) (16)
Insight into carrier lifetime impact on band-modulation devices (2017) (16)
Scaling MOSFETs to 10 nm: Coulomb Effects, Source Starvation, and Virtual Source (2009) (16)
Supply voltage strategies for minimizing the power of CMOS processors (2002) (15)
A High Speed, Low Power P-Channel Flash EEPROM Using Silicon Rich Oxide as Tunneling Dielectric (1992) (15)
Compact Modeling of Experimental n- and p-Channel FinFETs (2010) (15)
Direct measurement and characterization of n+ superhalo implants in a 120 nm gate-length Si metal–oxide–semiconductor field-effect transistor using cross-sectional scanning capacitance microscopy (2002) (15)
Experimental 0.1 mu m p-channel MOSFET with p/sup +/-polysilicon gate on 35 AA gate oxide (1993) (15)
Re-examination of the extraction of MOS interface-state density by C–V stretchout and conductance methods (2013) (15)
Circuit performance of double-gate SOI CMOS (2003) (15)
Low-Power Z2-FET Capacitorless 1T-DRAM (2017) (15)
High-Performance 0.07- m CMOS with 9.5-ps Gate Delay and 150 GHz (1997) (14)
A 2D analytical model for SCEs in MOSFETs with high-k gate dielectric (2010) (14)
Effect of Source–Drain Doping on Subthreshold Characteristics of Short-Channel DG MOSFETs (2017) (14)
SOI and bulk CMOS frequency dividers operating above 15 GHz (2001) (14)
High Performance 0.1/spl mu/m nMOSFET's with 10 ps/stage Delay (85 K) at 1.5 V Power Supply (1993) (14)
A 4 Mb Low-temperature DRAM (1991) (14)
A Continuous Semianalytic Current Model for DG and NW TFETs (2016) (14)
Voltage dependence of the MOSFET gate-to-source/drain overlap (1990) (13)
Modeling of DG MOSFET $I$ – $V$ Characteristics in the Saturation Region (2018) (13)
A framework for generic physics based double-gate MOSFET modeling (2003) (13)
A high performance BiCMOS technology using 0.25 mu m CMOS and double poly 47 GHz bipolar (1992) (13)
MOSFETs (2021) (12)
Ultra-low power 1T-DRAM in FDSOI technology (2017) (12)
Scaling Limit of CMOS Supply Voltage from Noise Margin Considerations (2006) (12)
Technology development & design for 22 nm InGaAs/InP-channel MOSFETs (2008) (12)
High transconductance 0.1 mu m pMOSFET (1992) (12)
Engineering High- k/SiGe Interface with ALD Oxide for Selective GeO x Reduction. (2019) (11)
A high-performance 0.5-&mu;m BiCMOS technology with 3.3-V CMOS devices (1990) (11)
0.5 Micron Gate CMOS Technology Using E-Beam/Optical Mix Lithography (1986) (11)
Compact modeling of multiple-gate MOSFETs (2008) (10)
Application of the Shunted Junction Model to Point-Contact Josephson Junctions (1974) (10)
Effect and extraction of series resistance in A 2 3 -InGaAs MOS with bulk-oxide trap (2013) (10)
Very Thin Nitride/Oxide Composite Gate Insulator for VLSI CMOS (1987) (10)
Physics-Based, Non-Charge-Sheet Compact Modeling of Double-Gate MOSFETs (2005) (10)
4 GHz and 13 GHz tuned amplifiers implemented in a 0.1 /spl mu/m CMOS technology on SOI and SOS substrates (1998) (9)
BiCMOS technology with 60 GHz n-p-n bipolar and 0.25 mu m CMOS (1992) (9)
Experimental Hardware Calibrated Compact Models for 50nm n-channel FinFETs (2007) (9)
Lithography and fabrication processes for sub‐100 nm scale complementary metal–oxide semiconductor (1995) (9)
Charge‐coupled devices in epitaxial HgCdTe/CdTe heterostructure (1981) (8)
Fabrication of ultrathin, highly uniform thin-film SOI MOSFETs with low series resistance using pattern-constrained epitaxy (1997) (8)
Ultra-thin, highly uniform thin film SOI MOSFET with low series resistance using pattern-constrained epitaxy (PACE) (1996) (8)
Editorial [EIC Y. Taur steps down] (2012) (8)
A Unified Two-Band Model for Oxide Traps and Interface States in MOS Capacitors (2015) (7)
Characterization of interface defects in ALD Al2O3/p-GaSb MOS capacitors using admittance measurements in range from kHz to GHz ☆ (2016) (7)
Submicron Tungsten Gate MOSFET with 10 nm Gate Oxide (1987) (6)
Very high performance 50 nm CMOS at low temperature (1999) (6)
A Non-GCA DG MOSFET Model Continuous into the Velocity Saturation Region (2019) (6)
Modeling Illumination Effects on n- and p-Type InGaAs MOS at Room and Low Temperatures (2014) (5)
Examination of Two-Band $E(k)$ Relations for Band-to-Band Tunneling (2016) (5)
Impact of carrier lifetime on Z2-FET operation (2017) (5)
A Short-Channel <inline-formula> <tex-math notation="LaTeX">$I$ </tex-math></inline-formula>–<inline-formula> <tex-math notation="LaTeX">$V$ </tex-math></inline-formula> Model for 2-D MOSFETs (2016) (5)
Ballistic-diffusive equations for multidimensional nanoscale heat conduction (2002) (5)
Scaling to 10 nm-bulk, SOI or double-gate MOSFETs? (2006) (5)
Design and fabrication of p-channel FET for 1-µm CMOS technology (1982) (5)
(Invited) Scaling FETs to 10 nm: Coulomb Effects, Source Starvation, and Virtual Source (2010) (5)
0.5µm-channel CMOS technology optimized for liquid-nitrogen-temperature operation (1986) (5)
Fully depleted 0.25 /spl mu/m MOSFETs on SOS, SIMOX and BSOI substrates (1994) (5)
An analytic model for heterojunction and homojunction tunnel FETs with 3D density of states (2015) (4)
Technology development & design for 22 nm InGaAs/InP-channel MOSFETs (2008) (4)
Compact Modeling of Short Channel Double-Gate MOSFETs (2006) (4)
Z2-FET DC hysteresis: Deep understanding and preliminary model (2017) (4)
A Josephson effect parametric amplifier at 36 GHz (1977) (4)
A highly latchup-immune 1 µm CMOS technology fabricated with 1 MeV ion implantation and self-aligned TiSi2 (1985) (3)
The mystery of the Z2-FET 1T-DRAM memory (2017) (3)
Z2-FET SPICE model: DC and memory operation (2017) (3)
High performance sub‐0.1 μm silicon n‐metal–oxide–semiconductor transistors with composite metal/polysilicon gates (1993) (3)
Static noise margin analysis of double-gate MOSFETs SRAM (2009) (3)
CMOS Device Design (2009) (3)
Understanding the Mechanism of Electronic Defects Suppression Enabled by Non-Idealities in Atomic Layer Deposition. (2019) (3)
Non-GCA modeling of near threshold I-V characteristics of DG MOSFETs (2020) (3)
Effect of Body Doping on the Scaling of Ultrathin SOI MOSFETs (2006) (3)
FEOL technology trend (1998) (2)
Millimeter‐wave generation at 110 GHz by laser modulation of a HgCdTe photodiode (1981) (2)
Comments to “A Distributive-Transconductance Model for Border Traps in III-V/High-k MOS Capacitors” (2013) (2)
NOISE DOWN-CONVERSION IN A PUMPED JOSEPHSON JUNCTION (1978) (2)
On the Log-Linear Inversion-Charge Relation for MOSFET Modeling (2022) (2)
Conversion gain in a Josephson effect mixer. Technical rept (1973) (2)
Effects of BOX thickness, silicon thickness, and backgate bias on SCE of ET-SOI MOSFETs (2021) (2)
A High Performance Liquid-Nitrogen CMOS SRAM Technology (1988) (2)
A view of nanoscale electronic devices (2003) (2)
Noise in Josephson effect mm-wave mixers (1975) (2)
A self-aligned 1-µm CMOS technology for VLSI (1983) (2)
Chapter 3 – CMOS Scaling to Nanometer Lengths (2003) (1)
Mobile ion gettering in passivated p+ polysilicon gates (1990) (1)
Progress on millimeter wave Josephson junction mixers (1978) (1)
A UCSD analytic TFET model (2015) (1)
Compact Modeling of Double-Gate and Nanowire MOSFETs (2010) (1)
CMOS technology evolution: from 1 /spl mu/m to 0.1 /spl mu/m (1995) (1)
Characteristics of a Josephson junction harmonic mixer with external pumping (1979) (1)
Probing the Limits of Silicon-Based Nanoelectronics (1995) (1)
What will end CMOS scaling - money or physics? (2004) (1)
Tunneling MOSFETs Based on III-V Staggered Heterojunctions (2010) (1)
New polysilicon disposable sidewall process for sub-50 nm CMOS (2001) (1)
Gate Dielectric Scaling to 2.0—1.0 nm: SiO2 and Silicon Oxynitride (2005) (1)
ULSI Scaling Toward 10 nm Gate-lengths: Challenges and Opportunities (2001) (1)
Conversion gain and noise in a Josephson effect mixer (1973) (1)
An All-Region I–V Model for 1-D Nanowire MOSFETs (2017) (0)
Corrections to "Fabrication of High-Quality p-MOSFET in Ge Grown Heteroepitaxially on Si" (2005) (0)
Simulation study of the noise figure of nanometer-gate nMOS transistors near the scaling limit (2007) (0)
GHz SOI CMOS Tuned Amplifier (2001) (0)
Invited talk: CMOS device scaling — Past, present, and future (2014) (0)
An Above Threshold Model for Short-Channel DG MOSFETs (2021) (0)
Changes in Editorial Board (2011) (0)
PERFORMANCE COMPARISON OF SCALED III-V AND Si BALLISTIC NANOWIRE MOSFETs (2009) (0)
0.5 μm CMOS Device Design and Characterization (1987) (0)
Feasibility Demonstration of New e-NVM Cells Suitable for Integration at 28 nm (0)
Analytic Charge Model for Double-Gate and Surrounding-Gate MOSFETs (2007) (0)
EDS Executive Director (2015) (0)
VB-4 charge-coupled devices in epitaxial HgCdTe/CdTe heterostructure (1981) (0)
A High-Performance 0.25-pm CMOS Technology: 11-Technolog y (1992) (0)
Foreword - Welcome to the 2004 Symposium on VLSI Technology (2004) (0)
Noise in Josephson mm-wave mixers (1975) (0)
Transistors and IC design (2001) (0)
Z2-FET memory for low power applications (2017) (0)
Prospects of Si ULSI Devices for the Next Ten Years (2001) (0)
Sub-Ambient Temperature Operation (2000) (0)
Kudos to Our Reviewers (2007) (0)
Challenges Near the Limit of CMOS Scaling (2004) (0)

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