Yuan Xie

Yuan Xie's AcademicInfluence.com Rankings

Yuan Xie

Engineering

#7111

World Rank

#8473

Historical Rank

Electrical Engineering

#2191

World Rank

#2297

Historical Rank

Applied Physics

#2393

World Rank

#2434

Historical Rank

engineering Degrees

Download Badge

Engineering

Yuan Xie's Degrees

Bachelors Electrical Engineering Tsinghua University

Why Is Yuan Xie Influential?

(Suggest an Edit or Addition)

(See a Problem?)

Yuan Xie's Published Works

Number of citations in a given year to any of this author's works

Total number of citations to an author for the works they published in a given year. This highlights publication of the most important work(s) by the author

Published Works

NVSim: A Circuit-Level Performance, Energy, and Area Model for Emerging Nonvolatile Memory (2012) (1003)
A novel architecture of the 3D stacked MRAM L2 cache for CMPs (2009) (445)
Design and Management of 3D Chip Multiprocessors Using Network-in-Memory (2006) (415)
Hybrid cache architecture with disparate memory technologies (2009) (376)
Circuit and microarchitecture evaluation of 3D stacking magnetic RAM (MRAM) as a universal memory replacement (2008) (335)
Design space exploration for 3D architectures (2006) (311)
Processor Design in 3D Die-Stacking Technologies (2007) (295)
A novel dimensionally-decomposed router for on-chip communication in 3D architectures (2007) (279)
Cache revive: Architecting volatile STT-RAM caches for enhanced performance in CMPs (2012) (274)
Design implications of memristor-based RRAM cross-point structures (2011) (235)
Kiln: Closing the performance gap between systems with and without persistence support (2013) (232)
MIRA: A Multi-layered On-Chip Interconnect Router Architecture (2008) (219)
Networks-on-chip in emerging interconnect paradigms: Advantages and challenges (2009) (195)
Interconnect and thermal-aware floorplanning for 3D microprocessors (2006) (192)
System-level cost analysis and design exploration for three-dimensional integrated circuits (3D ICs) (2009) (171)
NVMain 2.0: A User-Friendly Memory Simulator to Model (Non-)Volatile Memory Systems (2015) (168)
Reliability concerns in embedded system designs (2006) (155)
NVMain: An Architectural-Level Main Memory Simulator for Emerging Non-volatile Memories (2012) (152)
Leveraging 3D PCRAM technologies to reduce checkpoint overhead for future exascale systems (2009) (150)
Energy- and endurance-aware design of phase change memory caches (2010) (144)
Power attack resistant cryptosystem design: a dynamic voltage and frequency switching approach (2005) (137)
Impact of process variations on emerging memristor (2010) (136)
Simple but Effective Heterogeneous Main Memory with On-Chip Memory Controller Support (2010) (133)
Power and performance of read-write aware Hybrid Caches with non-volatile memories (2009) (127)
Modeling, Architecture, and Applications for Emerging Memory Technologies (2011) (126)
Test-access mechanism optimization for core-based three-dimensional SOCs (2008) (124)
Understanding the trade-offs in multi-level cell ReRAM memory design (2013) (123)
i2WAP: Improving non-volatile cache lifetime by reducing inter- and intra-set write variations (2013) (122)
SEAT-LA: a soft error analysis tool for combinational logic (2006) (122)
Adaptive placement and migration policy for an STT-RAM-based hybrid cache (2014) (120)
Thermal-aware floorplanning using genetic algorithms (2005) (118)
PCRAMsim: System-level performance, energy, and area modeling for Phase-Change RAM (2009) (112)
Half-DRAM: A high-bandwidth and low-power DRAM architecture from the rethinking of fine-grained activation (2014) (108)
Three-dimensional cache design exploration using 3DCacti (2005) (106)
Architecting on-chip interconnects for stacked 3D STT-RAM caches in CMPs (2011) (103)
A Case for Effic ient Hardware/Soft ware Cooperative Management of Storage and Memory (2013) (101)
Temperature-Aware Task Allocation and Scheduling for Embedded Multiprocessor Systems-on-Chip (MPSoC) Design (2006) (100)
Thermal-aware task allocation and scheduling for embedded systems (2005) (97)
Thermal-aware IP virtualization and placement for networks-on-chip architecture (2004) (97)
A hybrid SoC interconnect with dynamic TDMA-based transaction-less buses and on-chip networks (2006) (94)
Temperature-aware NBTI modeling and the impact of input vector control on performance degradation (2007) (90)
Reliability-aware Co-synthesis for Embedded Systems (2004) (89)
Soft Error Rate Analysis for Combinational Logic Using An Accurate Electrical Masking Model (2007) (89)
Design trade-offs for high density cross-point resistive memory (2012) (88)
Toward Increasing FPGA Lifetime (2008) (85)
Design Space Exploration for 3-D Cache (2008) (84)
Allocation and scheduling of conditional task graph in hardware/software co-synthesis (2001) (81)
On the efficacy of input Vector Control to mitigate NBTI effects and leakage power (2009) (80)
AdaMS: Adaptive MLC/SLC phase-change memory design for file storage (2011) (77)
Three-Dimensional Integrated Circuit Design: EDA, Design and Microarchitectures (2009) (76)
Variation-aware task allocation and scheduling for MPSoC (2007) (74)
LZW-based code compression for VLIW embedded systems (2004) (74)
Improving soft-error tolerance of FPGA configuration bits (2004) (74)
Processor Architecture Design Using 3D Integration Technology (2010) (72)
Fabrication Cost Analysis and Cost-Aware Design Space Exploration for 3-D ICs (2010) (72)
Cost-effective integration of three-dimensional (3D) ICs emphasizing testing cost analysis (2010) (71)
Scan chain design for three-dimensional integrated circuits (3D ICs) (2007) (70)
Reliability-centric high-level synthesis (2005) (69)
Access scheme of Multi-Level Cell Spin-Transfer Torque Random Access Memory and its optimization (2010) (68)
Code compression for VLIW processors using variable-to-fixed coding (2002) (67)
Three-dimensional integrated circuits (3D IC) Floorplan and Power/Ground Network Co-synthesis (2010) (66)
A low-power phase change memory based hybrid cache architecture (2008) (65)
Leakage Power and Circuit Aging Cooptimization by Gate Replacement Techniques (2011) (65)
Exploiting Heterogeneity for Energy Efficiency in Chip Multiprocessors (2011) (64)
FLAW: FPGA lifetime awareness (2006) (64)
Accurate stacking effect macro-modeling of leakage power in sub-100 nm circuits (2005) (63)
Energy-efficient multi-level cell phase-change memory system with data encoding (2011) (63)
Hybrid checkpointing using emerging nonvolatile memories for future exascale systems (2011) (62)
OAP: An obstruction-aware cache management policy for STT-RAM last-level caches (2013) (62)
Variable-Latency Adder (VL-Adder) Designs for Low Power and NBTI Tolerance (2010) (60)
3D-NonFAR: Three-dimensional non-volatile FPGA architecture using phase change memory (2010) (58)
Modeling of PMOS NBTI Effect Considering Temperature Variation (2007) (55)
Modeling Soft Errors at the Device and Logic Levels for Combinational Circuits (2009) (54)
Architecting Microprocessor Components in 3D Design Space (2007) (54)
The effect of threshold voltages on the soft error rate [memory and logic circuits] (2004) (54)
Low power memristor-based ReRAM design with Error Correcting Code (2012) (54)
Variation Impact on SER of Combinational Circuits (2007) (52)
Temperature-aware voltage islands architecting in system-on-chip design (2005) (52)
A code decompression architecture for VLIW processors (2001) (52)
Test-wrapper optimization for embedded cores in TSV-based three-dimensional SOCs (2009) (51)
A frequent-value based PRAM memory architecture (2011) (51)
Dependability analysis of nano-scale FinFET circuits (2006) (51)
3D optical networks-on-chip (NoC) for multiprocessor systems-on-chip (MPSoC) (2009) (49)
WADE: Writeback-aware dynamic cache management for NVM-based main memory system (2013) (46)
Variability-driven module selection with joint design time optimization and post-silicon tuning (2008) (46)
Electrical Characterization for Intertier Connections and Timing Analysis for 3-D ICs (2012) (45)
MorphCache: A Reconfigurable Adaptive Multi-level Cache hierarchy (2011) (45)
Emerging Memory Technologies: Design, Architecture, and Applications (2013) (45)
NoC-sprinting: Interconnect for fine-grained sprinting in the dark silicon era (2014) (45)
Design of cross-point metal-oxide ReRAM emphasizing reliability and cost (2013) (45)
Low-power dual-element memristor based memory design (2010) (44)
3D GPU architecture using cache stacking: Performance, cost, power and thermal analysis (2009) (42)
Guaranteeing Performance Yield in High-Level Synthesis (2006) (42)
Making B+-tree efficient in PCM-based main memory (2014) (41)
Design exploration of hybrid caches with disparate memory technologies (2010) (41)
Low power multi-level-cell resistive memory design with incomplete data mapping (2013) (40)
Scan-chain design and optimization for three-dimensional integrated circuits (2009) (39)
LOFT: A High Performance Network-on-Chip Providing Quality-of-Service Support (2010) (39)
Device-architecture co-optimization of STT-RAM based memory for low power embedded systems (2011) (39)
Designing energy-efficient NoC for real-time embedded systems through slack optimization (2013) (38)
PS3-RAM: A fast portable and scalable statistical STT-RAM reliability analysis method (2012) (37)
Thermal-aware reliability analysis for Platform FPGAs (2008) (37)
CREAM: A Concurrent-Refresh-Aware DRAM Memory architecture (2014) (36)
Future memory and interconnect technologies (2013) (35)
Optimizing bandwidth and power of graphics memory with hybrid memory technologies and adaptive data migration (2012) (35)
Moguls: A model to explore the memory hierarchy for bandwidth improvements (2011) (34)
Analysis and mitigation of lateral thermal blockage effect of through-silicon-via in 3D IC designs (2011) (33)
Code compression for embedded VLIW processors using variable-to-fixed coding (2006) (33)
Impact of process variation on soft error vulnerability for nanometer VLSI circuits (2005) (32)
Cost-aware three-dimensional (3D) many-core multiprocessor design (2010) (32)
Profile-Driven Selective Code Compression (2003) (31)
Reliability-centric hardware/software co-design (2005) (31)
Modeling TSV open defects in 3D-stacked DRAM (2010) (31)
Arithmetic unit design using 180nm TSV-based 3D stacking technology (2009) (30)
Variation-Aware Task and Communication Mapping for MPSoC Architecture (2011) (30)
Run-time technique for simultaneous aging and power optimization in GPGPUs (2014) (30)
Analysis of Subthreshold Finfet Circuits for Ultra-Low Power Design (2006) (29)
Temperature-Aware NBTI Modeling and the Impact of Standby Leakage Reduction Techniques on Circuit Performance Degradation (2011) (29)
3D Stacked Microprocessor: Are We There Yet? (2010) (28)
MAGE: Adaptive Granularity and ECC for resilient and power efficient memory systems (2012) (28)
A Variation Aware High Level Synthesis Framework (2008) (28)
Evaluation of using inductive/capacitive-coupling vertical interconnects in 3D network-on-chip (2010) (27)
Process-Variation-Aware Adaptive Cache Architecture and Management (2009) (27)
An ILP formulation for reliability-oriented high-level synthesis (2005) (27)
A 3D SoC design for H.264 application with on-chip DRAM stacking (2010) (26)
Architecting 3D vertical resistive memory for next-generation storage systems (2014) (26)
Automated mapping for reconfigurable single-electron transistor arrays (2011) (26)
Optimizing GPU energy efficiency with 3D die-stacking graphics memory and reconfigurable memory interface (2013) (26)
Modeling the Impact of Process Variation on Critical Charge Distribution (2006) (26)
Through Silicon Via Aware Design Planning for Thermally Efficient 3-D Integrated Circuits (2013) (26)
Bandwidth-aware reconfigurable cache design with hybrid memory technologies (2011) (25)
Designing scratchpad memory architecture with emerging STT-RAM memory technologies (2013) (25)
3DLAT: TSV-based 3D ICs crosstalk minimization utilizing Less Adjacent Transition code (2014) (25)
Enabling high-performance LPDDRx-compatible MRAM (2014) (25)
Modeling and design analysis of 3D vertical resistive memory — A low cost cross-point architecture (2014) (25)
Using multi-level cell STT-RAM for fast and energy-efficient local checkpointing (2014) (24)
Gate replacement techniques for simultaneous leakage and aging optimization (2009) (24)
Low-leakage robust SRAM cell design for sub-100nm technologies (2005) (24)
Exploration of 3D stacked L2 cache design for high performance and efficient thermal control (2009) (24)
Compression ratio and decompression overhead tradeoffs in code compression for VLIW architectures (2001) (24)
Point and discard: A hard-error-tolerant architecture for non-volatile last level caches (2012) (24)
A customized design of DRAM controller for on-chip 3D DRAM stacking (2010) (24)
Energy-efficient GPU design with reconfigurable in-package graphics memory (2012) (23)
TS-Router: On maximizing the Quality-of-Allocation in the On-Chip Network (2013) (23)
Exploring the vulnerability of CMPs to soft errors with 3D stacked non-volatile memory (2011) (23)
Assessment of Circuit Optimization Techniques Under NBTI (2013) (23)
Tolerating process variations in high-level synthesis using transparent latches (2009) (23)
Hierarchical Soft Error Estimation Tool (HSEET) (2008) (23)
On-chip Bus Thermal Analysis and Optimization (2006) (22)
Influence of leakage reduction techniques on delay/leakage uncertainty (2005) (22)
New-Age: A Negative Bias Temperature Instability-Estimation Framework for Microarchitectural Components (2009) (21)
Endurance-aware cache line management for non-volatile caches (2014) (21)
Comparative analysis of NBTI effects on low power and high performance flip-flops (2008) (21)
Thermal-aware power network design for IR drop reduction in 3D ICs (2012) (21)
Power optimization for FinFET-based circuits using genetic algorithms (2008) (21)
MNSIM 2.0: A Behavior-Level Modeling Tool for Memristor-based Neuromorphic Computing Systems (2020) (20)
Optimal topology exploration for application-specific 3D architectures (2006) (20)
Performance/Thermal-Aware Design of 3D-Stacked L2 Caches for CMPs (2012) (19)
3D-SWIFT: a high-performance 3D-stacked wide IO DRAM (2014) (19)
Delay and energy efficient data transmission for on-chip buses (2006) (19)
Emerging Memory Technologies (2019) (18)
Building energy-efficient multi-level cell STT-MRAM based cache through dynamic data-resistance encoding (2014) (18)
Editorial: ACM Transactions on Design Automation of Electronics Systems and Beyond (2014) (18)
A Synthesis Algorithm for Reconfigurable Single-Electron Transistor Arrays (2013) (18)
Code Compression for VLIW Embedded Systems Using a Self-Generating Table (2007) (17)
Impact of Cell Failure on Reliable Cross-Point Resistive Memory Design (2015) (17)
NoΔ: Leveraging delta compression for end-to-end memory access in NoC based multicores (2014) (17)
A framework for estimating NBTI degradation of microarchitectural components (2009) (17)
A Novel Gate-Level NBTI Delay Degradation Model with Stacking Effect (2007) (16)
Minimizing leakage power in aging-bounded high-level synthesis with design time multi-Vth assignment (2010) (16)
NBTI-aware statistical circuit delay assessment (2009) (16)
Inter-Disciplinary Research Challenges in Computer Systems for the 2020s (2018) (15)
Co-synthesis with custom ASICs (2000) (15)
Three-Dimensional Network-on-Chip Architecture (2010) (15)
Variation-aware resource sharing and binding in behavioral synthesis (2009) (15)
Exploring Design Space of 3 D NVM and eDRAM Caches Using DESTINY Tool (2015) (15)
Design of a nanosensor array architecture (2004) (15)
Thermomechanical stress-aware management for 3D IC designs (2013) (14)
Case Study of Reliability-Aware and Low-Power Design (2008) (14)
Cost-driven 3D integration with interconnect layers (2010) (14)
Design space exploration for 3D integrated circuits (2008) (14)
TSV-aware topology generation for 3D Clock Tree Synthesis (2013) (14)
Accelerating adaptive background subtraction with GPU and CBEA architecture (2010) (13)
An energy-efficient 3D CMP design with fine-grained voltage scaling (2011) (13)
Statistical High-Level Synthesis under Process Variability (2009) (13)
Mitigating electromigration of power supply networks using bidirectional current stress (2012) (13)
Enabling quality-of-service in nanophotonic network-on-chip (2011) (13)
Two-dimensional crosstalk avoidance codes (2008) (13)
Independently-Controlled-Gate FinFET 6T SRAM Cell Design for Leakage Current Reduction and Enhanced Read Access Speed (2014) (12)
Code Compression for VLIW Processors (2001) (12)
EECache: Exploiting design choices in energy-efficient last-level caches for chip multiprocessors (2014) (12)
Temperature-sensitive loop parallelization for chip multiprocessors (2005) (12)
Thermal-aware P/G TSV planning for IR drop reduction in 3D ICs (2013) (12)
Soft Error Rate Analysis for Combinational Logic Using an Accurate Electrical Masking Model (2007) (12)
Yield-aware time-efficient testing and self-fixing design for TSV-based 3D ICs (2012) (12)
Intrinsic NBTI-variability aware statistical pipeline performance assessment and tuning (2009) (12)
Code compression using variable-to-fixed coding based on arithmetic coding (2003) (11)
ILP-based scheme for timing variation-aware scheduling and resource binding (2008) (10)
Reliability-aware SOC voltage islands partition and floorplan (2006) (10)
WADE (2013) (9)
Variation Analysis of CAM Cells (2007) (9)
Three-dimensional Integrated Circuits: Design, EDA, and Architecture (2011) (9)
Efficient region-aware P/G TSV planning for 3D ICs (2014) (9)
Power Analysis Attack Resistance Engineering by Dynamic Voltage and Frequency Scaling (2012) (9)
Thermal-sustainable power budgeting for dynamic threading (2014) (8)
Exploration of Electrical and Novel Optical Chip-to-Chip Interconnects (2014) (8)
Stacking magnetic random access memory atop microprocessors: an architecture-level evaluation (2011) (8)
Modeling framework for cross-point resistive memory design emphasizing reliability and variability issues (2015) (8)
Design methodologies for 3D mixed signal integrated circuits: A practical 12-bit SAR ADC design case (2014) (8)
A Case Study of Incremental and Background Hybrid In-Memory Checkpointing (2010) (8)
Total Power Optimization for Combinational Logic Using Genetic Algorithms (2010) (8)
Enabling architectural innovations using non-volatile memory (2011) (7)
Effect of Power Optimizations on Soft Error Rate (2003) (7)
The impact of correlation between NBTI and TDDB on the performance of digital circuits (2011) (7)
Temperature-Aware NBTI Modeling Techniques in Digital Circuits (2009) (7)
A Novel Criticality Computation Method in Statistical Timing Analysis (2007) (7)
Simulation and analysis of P/G noise in TSV based 3D MPSoC (2010) (7)
3D memory stacking for fast checkpointing/restore applications (2010) (7)
Architectural benefits and design challenges for three-dimensional integrated circuits (2010) (6)
Die-stacking Architecture (2015) (6)
Evaluation of thermal-aware design techniques for microprocessors (2005) (6)
Cost-driven 3D design optimization with metal layer reduction technique (2013) (6)
System-Level 3D IC Cost Analysis and Design Exploration (2010) (6)
Temporal Performance Degradation under RTN: Evaluation and Mitigation for Nanoscale Circuits (2012) (6)
An instruction-level analytical power model for designing the low power systems on a chip (2005) (6)
A Probabilistic Model for Soft-Error Rate Estimation in Combinational Logic (2004) (6)
Emerging technologies and their impact on system design (2009) (5)
Whitespace-Aware TSV Arrangement in 3-D Clock Tree Synthesis (2013) (5)
Reliability-aware cross-point resistive memory design (2014) (5)
A criticality-driven microarchitectural three dimensional (3D) floorplanner (2009) (5)
Crosstalk-Aware Energy Efficient Encoding for Instruction Bus through Code Compression (2006) (5)
Guest Editors' Introduction: Opportunities and Challenges of 3D Integration (2009) (5)
3DHLS: Incorporating high-level synthesis in physical planning of three-dimensional (3D) ICs (2012) (5)
A Fault-Handling Methodology by Promoting Hardware Configurations via PageRank (2011) (4)
Energy and performance driven circuit design for emerging Phase-Change Memory (2010) (4)
Leakage-aware interconnect for on-chip network (2005) (4)
Leveraging on-chip DRAM stacking in an embedded 3D multi-core DSP system (2011) (4)
Parametric yield driven resource binding in behavioral synthesis with multi-Vth/Vdd library (2010) (4)
Code Decompression Unit Design for VLIW Embedded Processors (2007) (4)
Preventing STT-RAM Last-Level Caches from Port Obstruction (2014) (4)
F2BFLY: an on-chip free-space optical network with wavelength-switching (2011) (4)
ASICosyn: co-synthesis of conditional task graphs with custom ASICs (2001) (4)
A circuit-architecture co-optimization framework for exploring nonvolatile memory hierarchies (2013) (4)
Technology, CAD tools, and designs for emerging 3D integration technology (2008) (3)
Investigation and comparison of thermal distribution in synchronous and asynchronous 3D ICs (2009) (3)
On-Chip Hybrid Power Supply System for Wireless Sensor Nodes (2011) (3)
Exploring Design Space of 3D NVM and eDRAM Caches Using DESTINY Tool (open-source code) (2015) (3)
Modeling and design exploration of FBDRAM as on-chip memory (2012) (3)
SwimmingLane: A composite approach to mitigate voltage droop effects in 3D power delivery network (2014) (3)
Proceedings of the 21st edition of the great lakes symposium on Great lakes symposium on VLSI (2011) (3)
Microprocessor Design Using 3D Integration Technology (2011) (3)
Test-Access Solutions for Three-Dimensional SOCs (2008) (3)
Impact of Circuit Degradation on FPGA Design Security (2011) (3)
A circuit-architecture co-optimization framework for evaluating emerging memory hierarchies (2013) (3)
Rescuing RRAM-Based Computing From Static and Dynamic Faults (2021) (3)
Thermal-aware Design Considerations for Application-Specific Instruction Set Processor (2008) (3)
On-chip hybrid power supply system for wireless sensor nodes (2014) (2)
Power and area reduction using carbon nanotube bundle interconnect in global clock tree distribution network (2009) (2)
CheckerCore: enhancing an FPGA soft core to capture worst-case execution times (2009) (2)
Lazy Precharge: An overhead-free method to reduce precharge overhead for memory parallelism improvement of DRAM system (2013) (2)
Profile-driven selective code compression [embedded systems] (2003) (2)
System-level design space exploration for three-dimensional (3D) SoCs (2011) (2)
3D RRAM design and benchmark with 3d NAND FLASH (2014) (2)
Dswitch : Write-aware Dynamic Inclusion Property Switching for Emerging Asymmetric Memory Technologies (2016) (2)
Cost-Aware Lifetime Yield Analysis of Heterogeneous 3D On-chip Cache (2009) (2)
An Energy-Efficient 3D Stacked STT-RAM Cache Architecture for CMPs (2014) (2)
Adaptive power management in software radios using resolution adaptive analog to digital converters (2005) (2)
Embedded Multi-Processor System-on-chip (MPSoC) design considering process variations (2008) (2)
Augmenting Platform-Based Design with Synthesis Tools (2003) (2)
A Secure and Persistent Memory System for Non-volatile Memory (2019) (1)
Thermal-Aware 3D IC Designs (2011) (1)
MPU: Towards Bandwidth-abundant SIMT Processor via Near-bank Computing (2021) (1)
FPGA routing architecture analysis under variations (2007) (1)
Analysis of two code compression algorithms for embedded systems (2003) (1)
CPDI: Cross-power-domain interface circuit design in monolithic 3D technology (2013) (1)
Collaborative VLSI-CAD Instruction in the Digital Sandbox (2007) (1)
Leakage Optimized DECAP Design for FPGAs (2006) (1)
Wear-Leveling Techniques for Nonvolatile Memories (2014) (1)
Cost-Aware Exploration for Chiplet-Based Architecture with Advanced Packaging Technologies (2022) (1)
Parametric Yield-Driven Resource Binding in High-Level Synthesis with Multi-Vth/Vdd Library and Device Sizing (2012) (1)
Session details: 3-D integration challenges (2007) (0)
UNIVERSITY OF CALIFORNIA Santa Barbara Interconnect Fabric Reconfigurability for Network on Chip A Thesis submitted in partial satisfaction of the requirements for the degree Master of Science in Electrical and Computer Engineering by (2015) (0)
Compact models and model standard for 2.5D and 3D integration (2014) (0)
The Evaluation of a Novel Concurrent-Refresh-Aware DRAM System (2013) (0)
A cost benefit analysis: The impact of defect clustering on the necessity of pre-bond tests (2014) (0)
The Design and Implementation of Generalized Table Data Structure in DNA Computer (2015) (0)
Evaluation and mitigation of performance degradation under random telegraph noise for digital circuits (2013) (0)
Editorial- three-dimensional integrated circuits design (2011) (0)
TSV power supply array electromigration lifetime analysis in 3D ICS (2014) (0)
Low-Power Design of Emerging Memory Technologies (2012) (0)
1 Reliability-Centric High-Level Synthesis (2004) (0)
Special Issue on 3D IC Design and Test (2008) (0)
O 2 CDMA : Enable An Energy-Efficient OCDMA On The Chip (2011) (0)
Configurable accelerators for video analytics (2011) (0)
Testable cross-power domain interface (CPDI) circuit design in monolithic 3D technology (2014) (0)
Tutorial 1 Thermal-Aware Design Techniques for Nanometer VLSI Chip (2005) (0)
Exploiting Heterogeneity for Energy Efficiency in (2011) (0)
Influence of Stacked 3D Memory/Cache Architectures on GPUs (2011) (0)
Designing reliable circuit in the presence of soft errors (2005) (0)
Editorial ESL DesignMethodology (2015) (0)
D C ] 3 J an 2 01 9 A Secure and Persistent Memory System for Non-volatile Memory (2019) (0)
Redefining The Self-Normalization Property (2021) (0)
5.5 Alternative Computing Models (2019) (0)
What is 3D IC and what are the design challenges for 3D ICs? (2009) (0)
Chapter 2 3 D Integration Technology (2015) (0)
Session details: System power modeling and management (2010) (0)
Soft error rate measurements in semiconductor memories at Pennsylvania state university (2007) (0)
High-performance and Scalable Software-based NVMe Virtualization Mechanism with I/O Queues Passthrough (2023) (0)
Designing cool chips: low power and thermal-aware design methodologies (2006) (0)
A Cost Benefit Analysis: the Impact of Defect (2014) (0)
Editorial: Special issue on 3D integrated circuits and microarchitectures (2008) (0)
Tota I Power 0 pt i m izat i o n t h rough Si mu Ita neous I y Multiple-V,, Multiple-V,, Assignment and Device Sizing with Stack Forcing (2004) (0)
ESL Design Methodology (2012) (0)

This paper list is powered by the following services:

Yuan Xie's Academic­Influence.com Rankings

Yuan Xie's Degrees

Why Is Yuan Xie Influential?

Yuan Xie's Published Works

Published Works

Yuan Xie's AcademicInfluence.com Rankings