Yuan Xie
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Engineering Computer Science
Yuan Xie's Degrees
- PhD Electrical Engineering Princeton University
- Masters Electrical Engineering Princeton University
- Bachelors Electrical Engineering Tsinghua University
Why Is Yuan Xie Influential?
(Suggest an Edit or Addition)Yuan Xie's Published Works
Number of citations in a given year to any of this author's works
Total number of citations to an author for the works they published in a given year. This highlights publication of the most important work(s) by the author
Published Works
- PRIME: A Novel Processing-in-Memory Architecture for Neural Network Computation in ReRAM-Based Main Memory (2016) (1097)
- Towards artificial general intelligence with hybrid Tianjic chip architecture (2019) (427)
- Model Compression and Hardware Acceleration for Neural Networks: A Comprehensive Survey (2020) (352)
- Pinatubo: A processing-in-memory architecture for bulk bitwise operations in emerging non-volatile memories (2016) (326)
- Tackling the Qubit Mapping Problem for NISQ-Era Quantum Devices (2018) (289)
- Overcoming the challenges of crossbar resistive memory architectures (2015) (276)
- Cambricon: An Instruction Set Architecture for Neural Networks (2016) (269)
- DRISA: A DRAM-based Reconfigurable In-Situ Accelerator (2017) (261)
- DLAU: A Scalable Deep Learning Accelerator Unit on FPGA (2016) (217)
- Architecture exploration for ambient energy harvesting nonvolatile processors (2015) (211)
- HyGCN: A GCN Accelerator with Hybrid Architecture (2020) (155)
- A Hybrid solid-state storage architecture for the performance, energy consumption, and lifetime improvement (2010) (140)
- A Survey of Accelerator Architectures for Deep Neural Networks (2020) (135)
- DESTINY: A tool for modeling emerging 3D NVM and eDRAM caches (2015) (134)
- Ambient energy harvesting nonvolatile processors: From circuit to system (2015) (115)
- MNSIM: Simulation Platform for Memristor-Based Neuromorphic Computing System (2016) (115)
- Rethinking the performance comparison between SNNS and ANNS (2020) (113)
- FIRM: Fair and High-Performance Memory Control for Persistent Memory Systems (2014) (109)
- GraphH: A Processing-in-Memory Architecture for Large-Scale Graph Processing (2019) (108)
- TIME: A training-in-memory architecture for memristor-based deep neural networks (2017) (95)
- $L1$ -Norm Batch Normalization for Efficient Training of Deep Neural Networks (2018) (87)
- Power-efficient neural network with artificial dendrites (2020) (86)
- NEUTRAMS: Neural network transformation and co-design under neuromorphic hardware constraints (2016) (82)
- Mellow Writes: Extending Lifetime in Resistive Memories through Selective Slow Write Backs (2016) (79)
- Stuck-at Fault Tolerance in RRAM Computing Systems (2018) (78)
- Sparse Tensor Core: Algorithm and Hardware Co-Design for Vector-wise Sparse Neural Networks on Modern GPUs (2019) (74)
- Training High-Performance and Large-Scale Deep Neural Networks with Full 8-bit Integers (2019) (69)
- Software-Hardware Codesign for Efficient Neural Network Acceleration (2017) (62)
- DeepSniffer: A DNN Model Extraction Framework Based on Learning Architectural Hints (2020) (60)
- A 462GOPs/J RRAM-based nonvolatile intelligent processor for energy harvesting IoE system featuring nonvolatile logics and processing-in-memory (2017) (58)
- SCOPE: A Stochastic Computing Engine for DRAM-Based In-Situ Accelerator (2018) (58)
- Nonvolatile Processor Architecture Exploration for Energy-Harvesting Applications (2015) (56)
- Comparing SNNs and RNNs on Neuromorphic Vision Datasets: Similarities and Differences (2020) (56)
- Cost-effective design of scalable high-performance systems using active and passive interposers (2017) (53)
- A Study on Practically Unlimited Endurance of STT-MRAM (2017) (53)
- Analysis and Optimization of the Memory Hierarchy for Graph Processing Workloads (2019) (52)
- RADAR: A 3D-ReRAM based DNA Alignment Accelerator Architecture (2018) (51)
- Projection-based runtime assertions for testing and debugging Quantum programs (2020) (51)
- Incidental Computing on IoT Nonvolatile Processors (2017) (51)
- Bridge the Gap between Neural Networks and Neuromorphic Hardware with a Neural Network Compiler (2017) (50)
- SNrram: An Efficient Sparse Neural Network Computation Architecture Based on Resistive Random-Access Memory (2018) (50)
- Alleviating Irregularity in Graph Analytics Acceleration: a Hardware/Software Co-Design Approach (2019) (49)
- A 16Mb dual-mode ReRAM macro with sub-14ns computing-in-memory and memory functions enabled by self-write termination scheme (2017) (47)
- OSCAR: Orchestrating STT-RAM cache traffic for heterogeneous CPU-GPU architectures (2016) (46)
- GNNAdvisor: An Adaptive and Efficient Runtime System for GNN Acceleration on GPUs (2020) (43)
- DimNoC: A dim silicon approach towards power-efficient on-chip network (2015) (43)
- MEDAL: Scalable DIMM based Near Data Processing Accelerator for DNA Seeding Algorithm (2019) (43)
- Tianjic: A Unified and Scalable Chip Bridging Spike-Based and Continuous Neural Computation (2020) (43)
- TIME: A Training-in-Memory Architecture for RRAM-Based Deep Neural Networks (2019) (42)
- FPSA: A Full System Stack Solution for Reconfigurable ReRAM-based NN Accelerator Architecture (2019) (41)
- Timely: Pushing Data Movements And Interfaces In Pim Accelerators Towards Local And In Time Domain (2020) (41)
- Learning the sparsity for ReRAM: mapping and pruning sparse neural network for ReRAM based accelerator (2019) (40)
- Towards Efficient Superconducting Quantum Processor Architecture Design (2019) (40)
- Energy Efficient RRAM Spiking Neural Network for Real Time Classification (2015) (39)
- iPIM: Programmable In-Memory Image Processing Accelerator Using Near-Bank Architecture (2020) (39)
- Characterizing and Understanding GCNs on GPU (2020) (37)
- SmartExchange: Trading Higher-cost Memory Storage/Access for Lower-cost Computation (2020) (37)
- Computation-oriented fault-tolerance schemes for RRAM computing systems (2017) (36)
- Neural Network Model Extraction Attacks in Edge Devices by Hearing Architectural Hints (2019) (36)
- HitNet: Hybrid Ternary Recurrent Neural Network (2018) (35)
- Memory Trojan Attack on Neural Network Accelerators (2019) (35)
- Core vs. uncore: The heart of darkness (2015) (34)
- Nonvolatile Processor Architectures: Efficient, Reliable Progress with Unstable Power (2016) (34)
- Leveraging 3D technologies for hardware security: Opportunities and challenges (2016) (33)
- Hybrid Drowsy SRAM and STT-RAM Buffer Designs for Dark-Silicon-Aware NoC (2016) (32)
- Die Stacking Is Happening (2018) (31)
- Cost analysis and cost-driven IP reuse methodology for SoC design based on 2.5D/3D integration (2016) (31)
- Dynamic Sparse Graph for Efficient Deep Learning (2018) (30)
- Crossbar-Aware Neural Network Pruning (2018) (30)
- SuperMem: Enabling Application-transparent Secure Persistent Memory with Low Overheads (2019) (30)
- IRONMAN: GNN-assisted Design Space Exploration in High-Level Synthesis via Reinforcement Learning (2021) (29)
- Spendthrift: Machine learning based resource and frequency scaling for ambient energy harvesting nonvolatile processors (2017) (28)
- NVSim-CAM: A circuit-level simulator for emerging nonvolatile memory based Content-Addressable Memory (2016) (27)
- Architecture design with STT-RAM: Opportunities and challenges (2016) (27)
- GNNAdvisor: An Efficient Runtime System for GNN Acceleration on GPUs (2020) (27)
- Impact of Write Pulse and Process Variation on 22 nm FinFET-Based STT-RAM Design: A Device-Architecture Co-Optimization Approach (2015) (24)
- Comprehensive SNN Compression Using ADMM Optimization and Activity Regularization (2019) (24)
- Rubik: A Hierarchical Architecture for Efficient Graph Neural Network Training (2021) (24)
- SpaceA: Sparse Matrix Vector Multiplication on Processing-in-Memory Accelerator (2021) (23)
- Exploring Adversarial Attack in Spiking Neural Networks With Spike-Compatible Gradient (2020) (22)
- LAP: Loop-Block Aware Inclusion Properties for Energy-Efficient Asymmetric Last Level Caches (2016) (22)
- QGAN: Quantized Generative Adversarial Networks (2019) (22)
- Dynamic machine learning based matching of nonvolatile processor microarchitecture to harvested energy profile (2015) (21)
- Building energy-efficient multi-level cell STT-RAM caches with data compression (2017) (21)
- Performance Evaluation and Optimization of HBM-Enabled GPU for Data-Intensive Applications (2017) (20)
- Buri: Scaling Big-Memory Computing with Hardware-Based Memory Expansion (2015) (20)
- Overview of 3-D Architecture Design Opportunities and Techniques (2017) (20)
- PXNOR-BNN: In/With Spin-Orbit Torque MRAM Preset-XNOR Operation-Based Binary Neural Networks (2019) (20)
- ProactiveDRAM: A DRAM-initiated retention management scheme (2014) (19)
- CNNLab: a Novel Parallel Framework for Neural Networks using GPU and FPGA-a Practical Study with Trade-off Analysis (2016) (19)
- EGEMM-TC: accelerating scientific computing on tensor cores with extended precision (2021) (19)
- Redesigning software and systems for non-volatile processors on self-powered devices (2016) (19)
- Memory and Storage System Design with Nonvolatile Memory Technologies (2015) (18)
- Thermal-aware 3D design for side-channel information leakage (2016) (18)
- Paulihedral: a generalized block-wise compiler optimization framework for Quantum simulation kernels (2021) (18)
- Dynamic Power and Energy Management for Energy Harvesting Nonvolatile Processor Systems (2017) (18)
- A Survey of Machine Learning for Computer Architecture and Systems (2021) (17)
- TETRIS: TilE-matching the TRemendous Irregular Sparsity (2018) (17)
- There and back again: Optimizing the interconnect in networks of memory cubes (2017) (17)
- Evolver: A Deep Learning Processor With On-Device Quantization–Voltage–Frequency Tuning (2021) (17)
- Fulcrum: A Simplified Control and Access Mechanism Toward Flexible and Practical In-Situ Accelerators (2020) (17)
- Optimizing the NoC Slack Through Voltage and Frequency Scaling in Hard Real-Time Embedded Systems (2014) (16)
- Scalable memory fabric for silicon interposer-based multi-core systems (2016) (16)
- Memory that never forgets: emerging nonvolatile memory and the implication for architecture design (2018) (16)
- A Write-Aware STTRAM-Based Register File Architecture for GPGPU (2015) (15)
- A unified memory network architecture for in-memory computing in commodity servers (2016) (15)
- Effective Model Sparsification by Scheduled Grow-and-Prune Methods (2021) (15)
- Persistence Parallelism Optimization: A Holistic Approach from Memory Bus to RDMA Network (2018) (15)
- SemiMap: A Semi-Folded Convolution Mapping for Speed-Overhead Balance on Crossbars (2020) (15)
- PS3-RAM: A Fast Portable and Scalable Statistical STT-RAM Reliability/Energy Analysis Method (2014) (15)
- Securing Emerging Nonvolatile Main Memory With Fast and Energy-Efficient AES In-Memory Implementation (2018) (14)
- NVSim-VXs: An improved NVSim for variation aware STT-RAM simulation (2016) (14)
- DUET: Boosting Deep Neural Network Efficiency on Dual-Module Architecture (2020) (14)
- Practical Attacks on Deep Neural Networks by Memory Trojaning (2020) (13)
- Rubik: A Hierarchical Architecture for Efficient Graph Learning (2020) (13)
- Security Threats and Countermeasures in Three-Dimensional Integrated Circuits (2017) (13)
- DLUX: A LUT-Based Near-Bank Accelerator for Data Center Deep Learning Training Workloads (2020) (13)
- fuseGNN: Accelerating Graph Convolutional Neural Network Training on GPGPU (2020) (13)
- An Adaptive 3T-3MTJ Memory Cell Design for STT-MRAM-Based LLCs (2018) (12)
- ODESY: A novel 3T-3MTJ cell design with optimized area density, scalability and latency (2016) (12)
- Thermomechanical Stress-Aware Management for 3-D IC Designs (2017) (12)
- NEST: DIMM based Near-Data-Processing Accelerator for K-mer Counting (2020) (12)
- Adapting $\text{B}^{+}$ -Tree for Emerging Nonvolatile Memory-Based Main Memory (2016) (11)
- A Comprehensive and Modularized Statistical Framework for Gradient Norm Equality in Deep Neural Networks (2020) (11)
- DASM: Data-Streaming-Based Computing in Nonvolatile Memory Architecture for Embedded System (2019) (11)
- Understanding GNN Computational Graph: A Coordinated Computation, IO, and Memory Perspective (2021) (11)
- SANQ: A Simulation Framework for Architecting Noisy Intermediate-Scale Quantum Computing System (2019) (11)
- AIM: Fast and energy-efficient AES in-memory implementation for emerging non-volatile main memory (2018) (10)
- Structurally Sparsified Backward Propagation for Faster Long Short-Term Memory Training (2018) (10)
- Mitigating BTI-Induced Degradation in STT-MRAM Sensing Schemes (2018) (10)
- Leveraging nonvolatility for architecture design with emerging NVM (2015) (10)
- PRESCOTT: Preset-based cross-point architecture for spin-orbit-torque magnetic random access memory (2017) (10)
- Training Long Short-Term Memory With Sparsified Stochastic Gradient Descent (2017) (9)
- Effective and Efficient Batch Normalization Using a Few Uncorrelated Data for Statistics Estimation (2020) (9)
- Cost and Thermal Analysis of High-Performance 2.5D and 3D Integrated Circuit Design Space (2016) (9)
- H2Learn: High-Efficiency Learning Accelerator for High-Accuracy Spiking Neural Networks (2021) (9)
- GraphIA: an in-situ accelerator for large-scale graph processing (2018) (9)
- Fast Object Tracking on a Many-Core Neural Network Chip (2018) (8)
- NeuroMeter: An Integrated Power, Area, and Timing Modeling Framework for Machine Learning Accelerators Industry Track Paper (2021) (8)
- Parana: A Parallel Neural Architecture Considering Thermal Problem of 3D Stacked Memory (2019) (8)
- CORN: In-Buffer Computing for Binary Neural Network (2019) (8)
- IAA: Incidental Approximate Architectures for Extremely Energy-Constrained Energy Harvesting Scenarios using IoT Nonvolatile Processors (2018) (7)
- Cost-efficient 3D Integration to Hinder Reverse Engineering During and After Manufacturing (2018) (7)
- Packet Pump: Overcoming Network Bottleneck in On-Chip Interconnects for GPGPUs* (2018) (7)
- Computation on Sparse Neural Networks: an Inspiration for Future Hardware (2020) (7)
- Boosting Deep Neural Network Efficiency with Dual-Module Inference (2020) (7)
- Crane: Mitigating Accelerator Under-utilization Caused by Sparsity Irregularities in CNNs (2020) (7)
- Fine-granularity tile-level parallelism in non-volatile memory architecture with two-dimensional bank subdivision (2016) (7)
- Fast Search of the Optimal Contraction Sequence in Tensor Networks (2021) (7)
- Heterogeneous architecture design with emerging 3D and non-volatile memory technologies (2015) (7)
- Poq: Projection-based Runtime Assertions for Debugging on a Quantum Computer (2019) (7)
- Near-Data Acceleration of Privacy-Preserving Biomarker Search with 3D-Stacked Memory (2019) (7)
- Core Placement Optimization for Multi-chip Many-core Neural Network Systems with Reinforcement Learning (2020) (6)
- SAGA-Bench: Software and Hardware Characterization of Streaming Graph Analytics Workloads (2020) (6)
- An Instruction Set Architecture for Machine Learning (2019) (6)
- DARB: A Density-Adaptive Regular-Block Pruning for Deep Neural Networks (2020) (6)
- NNBench-X: Benchmarking and Understanding Neural Network Workloads for Accelerator Designs (2019) (6)
- Proceedings of the 2016 International Symposium on Low Power Electronics and Design (2013) (6)
- Building and Optimizing MRAM-Based Commodity Memories (2014) (5)
- Building a Low Latency, Highly Associative DRAM Cache with the Buffered Way Predictor (2016) (5)
- Self-powered wearable sensor node: Challenges and opportunities (2015) (5)
- DIMMining: pruning-efficient and parallel graph mining on near-memory-computing (2022) (5)
- SEAL-lab Technical Report – No . 2015-001 ( April 29 , 2016 ) Processing-in-Memory in ReRAM-based Main Memory (2016) (5)
- Memory-Bound Proof-of-Work Acceleration for Blockchain Applications (2019) (5)
- EECache: A Comprehensive Study on the Architectural Design for Energy-Efficient Last-Level Caches in Chip Multiprocessors (2015) (5)
- SEALing Neural Network Models in Encrypted Deep Learning Accelerators (2021) (4)
- Exploring Core and Cache Hierarchy Bottlenecks in Graph Processing Workloads (2018) (4)
- Neural network transformation under hardware constraints (2016) (4)
- Balancing Memory Accesses for Energy-Efficient Graph Analytics Accelerators (2019) (4)
- IronMan-Pro: Multiobjective Design Space Exploration in HLS via Reinforcement Learning and Graph Neural Network-Based Modeling (2023) (4)
- Eliminating Redundant Computation in Noisy Quantum Computing Simulation (2020) (4)
- Leveraging emerging nonvolatile memory in high-level synthesis with loop transformations (2015) (4)
- BACH: A Bandwidth-Aware Hybrid Cache Hierarchy Design with Nonvolatile Memories (2016) (4)
- Towards a polynomial algorithm for optimal contraction sequence of tensor networks from trees. (2019) (4)
- Investigation of Cost-Optimal Network-on-Chip for Passive and Active Interposer Systems (2019) (4)
- A Real-Time and Energy-Efficient Implementation of Difference-of-Gaussian with Flexible Thin-Film Transistors (2016) (4)
- Hardware-Enabled Efficient Data Processing With Tensor-Train Decomposition (2021) (3)
- 3D Integration Technology (2015) (3)
- TSocket: Thermal Sustainable Power Budgeting (2016) (3)
- CNNWire: Boosting Convolutional Neural Network with Winograd on ReRAM based Accelerators (2019) (3)
- A Systematic View of Leakage Risks in Deep Neural Network Systems (2021) (3)
- Taming Unstructured Sparsity on GPUs via Latency-Aware Optimization (2020) (3)
- Invited: Efficient System Architecture in the Era of Monolithic 3D: Dynamic Inter-Tier Interconnect and Processing-in-Memory (2019) (3)
- History-Assisted Adaptive-Granularity Caches (HAAG$) for High Performance 3D DRAM Architectures (2015) (3)
- Heuristic adaptability to input dynamics for SpMM on GPUs (2022) (3)
- Network-on-Chip Design Guidelines for Monolithic 3-D Integration (2019) (3)
- Hardware Acceleration for GCNs via Bidirectional Fusion (2021) (3)
- Nonvolatile memory allocation and hierarchy optimization for high-level synthesis (2015) (3)
- LOSTIN: Logic Optimization via Spatio-Temporal Information with Hybrid Graph Models (2022) (2)
- NEOFog (2018) (2)
- Overcoming the Memory Hierarchy Inefficiencies in Graph Processing Applications (2021) (2)
- There and Back Again (2017) (2)
- Designing vertical bandwidth reconfigurable 3D NoCs for many core systems (2014) (2)
- Exploring memory controller configurations for many-core systems with 3D stacked DRAMs (2015) (2)
- A Novel, Efficient Implementation of a Local Binary Convolutional Neural Network (2021) (2)
- Power Profiling of Modern Die-Stacked Memory (2019) (2)
- SEALing Neural Network Models in Secure Deep Learning Accelerators (2020) (2)
- TiAcc: Triangle-inequality based Hardware Accelerator for K-means on FPGAs (2021) (2)
- CRISP: Center for Research on Intelligent Storage and Processing-in-Memory (2019) (2)
- In-memory multiplication engine with SOT-MRAM based stochastic computing (2018) (2)
- INVITED: Computation on Sparse Neural Networks and its Implications for Future Hardware (2020) (2)
- Efficient Sparse Matrix Kernels based on Adaptive Workload-Balancing and Parallel-Reduction (2021) (2)
- NNBench-X: A Benchmarking Methodology for Neural Network Accelerator Designs (2019) (2)
- Accelerating CPU-Based Sparse General Matrix Multiplication With Binary Row Merging (2022) (1)
- EECache (2015) (1)
- PLSAV: Parallel loop searching and verifying for loop closure detection (2021) (1)
- A Case for 3D Integrated System Design for Neuromorphic Computing & AI Applications (2020) (1)
- STPAcc: Structural TI-Based Pruning for Accelerating Distance-Related Algorithms on CPU-FPGA Platforms (2021) (1)
- Load-balanced Gather-scatter Patterns for Sparse Deep Neural Networks (2021) (1)
- Buri (2015) (1)
- Neural Network Pruning for Crossbar Architecture (2018) (1)
- Research on low-power neural network computing accelerator (2019) (1)
- Adaptive Burst-Writes (ABW) (2015) (1)
- MPU-Sim: A Simulator for In-DRAM Near-Bank Processing Architectures (2022) (1)
- Processing-In-Memory Architecture Design for Accelerating Neuro-Inspired Algorithms (2017) (1)
- SEAL-lab Technical Report – No . 2015-001 ( November 30 , 2015 ) Processing-in-Memory in ReRAM-based Main Memory (2015) (1)
- Using Multiple-Input NEMS for Parallel A/D Conversion and Image Processing (2015) (1)
- NoC-Aware Computational Sprinting (2017) (0)
- A one-for-all and o(v log(v ))-cost solution for parallel merge style operations on sorted key-value arrays (2022) (0)
- Batch Normalization Sampling (2018) (0)
- Recap of the 39th Edition of the International Conference on Computer-Aided Design (ICCAD 2020) (2021) (0)
- BEACON: Scalable Near-Data-Processing Accelerators for Genome Analysis near Memory Pool with the CXL Support (2022) (0)
- Blackcomb2: Hardware-Software Co-design for Nonvolatile Memory in Exascale Systems (2018) (0)
- Session details: Keynote address (2014) (0)
- NNBench-X (2020) (0)
- DARB: A Density-Aware Regular-Block Pruning for Deep Neural Networks (2019) (0)
- Utilizing 3D ICs in architectures for neural networks (2016) (0)
- Dual-module Inference for Efficient Recurrent Neural Networks (2019) (0)
- Introduction to the Special Issue on Reliable, Resilient, and Robust Design of Circuits and Systems (2015) (0)
- AccD: A Compiler-based Framework for Accelerating Distance-related Algorithms on CPU-FPGA Platforms (2019) (0)
- POSTER: Bridge the Gap Between Neural Networks and Neuromorphic Hardware (2017) (0)
- Memristor Hardware-Friendly Reinforcement Learning (2020) (0)
- SaARSP: An Architecture for Systolic-Array Acceleration of Recurrent Spiking Neural Networks (2022) (0)
- NMTSim: Transaction-Command Based Simulator for New Memory Technology Devices (2020) (0)
- QGAN: Quantize Generative Adversarial Networks to Extreme low-bits (2019) (0)
- SPCIM: Sparsity-Balanced Practical CIM Accelerator With Optimized Spatial-Temporal Multi-Macro Utilization (2023) (0)
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