Mary Jane Irwin

Q: What Schools Are Affiliated With Mary Jane Irwin

Mary Jane Irwin is affiliated with the following schools: University of Memphis, Pennsylvania State University

Mary Jane Irwin's AcademicInfluence.com Rankings

Mary Jane Irwin

Computer Science

#538

World Rank

#558

Historical Rank

#294

USA Rank

Database

#1132

World Rank

#1189

Historical Rank

#315

USA Rank

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Computer Science

Why Is Mary Jane Irwin Influential?

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According to Wikipedia, Mary Jane Irwin is an Emerita Evan Pugh Professor in the Department of Computer Science and Engineering at Pennsylvania State University. She has been on the faculty at Penn State since 1977. She is an international expert in computer architecture. Her research and teaching interests include computer architecture, embedded and mobile computing systems design, power and reliability aware design, and emerging technologies in computing systems.

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Mary Jane Irwin's Published Works

Number of citations in a given year to any of this author's works

Total number of citations to an author for the works they published in a given year. This highlights publication of the most important work(s) by the author

Published Works

Leakage Current: Moore's Law Meets Static Power (2003) (1259)
The design and use of simplePower: a cycle-accurate energy estimation tool (2000) (517)
Analysis of error recovery schemes for networks on chips (2005) (352)
VLSI architectures for the discrete wavelet transform (1995) (343)
Energy-driven integrated hardware-software optimizations using SimplePower (2000) (341)
Dynamic management of scratch-pad memory space (2001) (272)
Area-time-power tradeoffs in parallel adders (1996) (242)
Using complete machine simulation for software power estimation: the SoftWatt approach (2002) (234)
Fault tolerant algorithms for network-on-chip interconnect (2004) (230)
Influence of compiler optimizations on system power (2000) (219)
Interconnect and thermal-aware floorplanning for 3D microprocessors (2006) (192)
DRAM energy management using software and hardware directed power mode control (2001) (190)
Studying energy trade offs in offloading computation/compilation in Java-enabled mobile devices (2004) (161)
Scheduler-based DRAM energy management (2002) (148)
Techniques for low energy software (1997) (147)
Reducing leakage energy in FPGAs using region-constrained placement (2004) (142)
Soft error and energy consumption interactions: a data cache perspective (2004) (135)
An edge-based heuristic for Steiner routing (1994) (130)
Evaluating run-time techniques for leakage power reduction (2002) (129)
Adaptive set pinning: managing shared caches in chip multiprocessors (2008) (127)
SEAT-LA: a soft error analysis tool for combinational logic (2006) (122)
Hardware and Software Techniques for Controlling DRAM Power Modes (2001) (119)
Thermal-aware floorplanning using genetic algorithms (2005) (118)
Some issues in gray code addressing (1996) (110)
Energy characterization based on clustering (1996) (109)
Three-dimensional cache design exploration using 3DCacti (2005) (106)
A Dual-VDD Low Power FPGA Architecture (2004) (105)
Energy optimization techniques in cluster interconnects (2003) (99)
Embedded hardware face detection (2004) (98)
Leakage energy management in cache hierarchies (2002) (98)
Thermal-aware task allocation and scheduling for embedded systems (2005) (97)
Thermal-aware IP virtualization and placement for networks-on-chip architecture (2004) (97)
Energy-conscious compilation based on voltage scaling (2002) (95)
A clock power model to evaluate impact of architectural and technology optimizations (2002) (91)
Reliability-aware Co-synthesis for Embedded Systems (2004) (89)
Compiler-directed instruction cache leakage optimization (2002) (89)
Transistor sizing for low power CMOS circuits (1996) (85)
Toward Increasing FPGA Lifetime (2008) (85)
Digit-Pipelined Arnthmetic as Illustrated by the Paste-Up System: A Tutorial (1987) (85)
Design Space Exploration for 3-D Cache (2008) (84)
Masking the Energy Behavior of DES Encryption (2003) (84)
Optimizing sensor movement planning for energy efficiency (2011) (83)
Exploiting barriers to optimize power consumption of CMPs (2005) (80)
A parallel architecture for hardware face detection (2006) (78)
A compiler-based approach for dynamically managing scratch-pad memories in embedded systems (2004) (78)
Soft errors issues in low-power caches (2005) (75)
Improving soft-error tolerance of FPGA configuration bits (2004) (74)
Exploiting VLIW schedule slacks for dynamic and leakage energy reduction (2001) (72)
Power-delay characteristics of CMOS adders (1994) (70)
Priority Scheduling in Digital Microfluidics-Based Biochips (2006) (69)
A novel migration-based NUCA design for Chip Multiprocessors (2008) (68)
Compiler-directed instruction duplication for soft error detection (2005) (68)
Interplay of energy and performance for disk arrays running transaction processing workloads (2003) (67)
Heap compression for memory-constrained Java environments (2003) (67)
vEC: virtual energy counters (2001) (66)
A low-power phase change memory based hybrid cache architecture (2008) (65)
Instruction level power profiling (1996) (64)
Adaptive error protection for energy efficiency (2003) (64)
Logic synthesis for field-programmable gate arrays (1994) (64)
Energy-oriented compiler optimizations for partitioned memory architectures (2000) (63)
A SIMD solution to the sequence comparison problem on the MGAP (1994) (60)
On the Effects of Process Variation in Network-on-Chip Architectures (2010) (60)
Characterization and modeling of run-time techniques for leakage power reduction (2004) (59)
A crosstalk aware interconnect with variable cycle transmission (2004) (59)
Impact of scaling on the effectiveness of dynamic power reduction schemes (2002) (59)
Transistor sizing for minimizing power consumption of CMOS circuits under delay constraint (1995) (56)
Analyzing soft errors in leakage optimized SRAM design (2003) (56)
Tuning garbage collection in an embedded Java environment (2002) (55)
Modeling Soft Errors at the Device and Logic Levels for Combinational Circuits (2009) (54)
The effect of threshold voltages on the soft error rate [memory and logic circuits] (2004) (54)
Architecting Microprocessor Components in 3D Design Space (2007) (54)
Plagiarism on the rise (2006) (53)
Variation Impact on SER of Combinational Circuits (2007) (52)
Architecture-level power estimation and design experiments (2001) (52)
Compiler support for reducing leakage energy consumption (2003) (52)
Analysis of soft error rate in flip-flops and scannable latches (2003) (51)
ELM-A Fast Addition Algorithm Discovered by a Program (1992) (48)
Exploring technology alternatives for nano-scale FPGA interconnects (2005) (47)
Instruction Scheduling for Low Power (2004) (47)
Compiler-guided leakage optimization for banked scratch-pad memories (2005) (47)
Impact of technology scaling in the clock system power (2002) (46)
Implications of technology scaling on leakage reduction techniques (2003) (46)
Discrete wavelet transforms in VLSI (1992) (46)
MorphCache: A Reconfigurable Adaptive Multi-level Cache hierarchy (2011) (45)
A parallel architecture for secure FPGA symmetric encryption (2004) (45)
Compiler-assisted soft error detection under performance and energy constraints in embedded systems (2009) (45)
Total power optimization through simultaneously multiple-vDD multiple-vTH assignment and device sizing with stack forcing (2004) (44)
Adapting instruction level parallelism for optimizing leakage in VLIW architectures (2003) (44)
Exploiting program hotspots and code sequentiality for instruction cache leakage management (2003) (42)
Accurate Estimation of Combinational Circuit Activity (1995) (42)
Energy Behavior of Java Applications from the Memory Perspective (2001) (41)
Compiler optimizations for low power systems (2002) (41)
Masking the energy behavior of DES encryption [smart cards] (2003) (41)
A helper thread based EDP reduction scheme for adapting application execution in CMPs (2008) (40)
Compiler-directed array interleaving for reducing energy in multi-bank memories (2002) (38)
A generic reconfigurable neural network architecture as a network on chip (2004) (37)
Tuning garbage collection for reducing memory system energy in an embedded java environment (2002) (36)
Compiler-directed thermal management for VLIW functional units (2006) (36)
Power-aware partitioned cache architectures (2001) (36)
Ultra Low Power Circuit Design Using Tunnel FETs (2012) (36)
Evaluating Integrated Hardware-Software Optimizations Using a Unified Energy Estimation Framework (2003) (36)
An alternative architecture for on-chip global interconnect: segmented bus power modeling (1998) (35)
Partitioned instruction cache architecture for energy efficiency (2003) (35)
Clock power issues in system-on-a-chip designs (1999) (34)
Power comparisons for barrel shifters (1996) (34)
Core vs. uncore: The heart of darkness (2015) (34)
Cache topology aware computation mapping for multicores (2010) (34)
Regular, area-time efficient carry-lookahead adders (1985) (34)
Banked scratch-pad memory management for reducing leakage energy consumption (2004) (33)
Validation of an architectural level power analysis technique (1998) (33)
A detailed analysis of MediaBench (1999) (32)
Exploring Wakeup-Free Instruction Scheduling (2004) (32)
A novel low power CAM design (2001) (32)
A holistic approach to designing energy-efficient cluster interconnects (2005) (32)
Implementing LDPC decoding on network-on-chip (2005) (31)
An extended addressing mode for low power (1997) (31)
Exploiting communication complexity for multilevel logic synthesis (1990) (30)
Arithmetic unit design using 180nm TSV-based 3D stacking technology (2009) (30)
Optimizing sensor movement planning for energy efficiency (2005) (29)
A Two-Dimensional, Distributed Logic Architecture (1991) (28)
ChipPower: an architecture-level leakage simulator (2004) (28)
Instruction scheduling based on energy and performance constraints (2000) (28)
Reducing NoC energy consumption through compiler-directed channel voltage scaling (2006) (27)
Process-Variation-Aware Adaptive Cache Architecture and Management (2009) (27)
The Arithmetic Cube (1987) (27)
EAC: a compiler framework for high-level energy estimation and optimization (2002) (26)
The logarithmic number system for strength reduction in adaptive filtering (1998) (26)
Image processing with the MGAP: a cost effective solution (1993) (26)
PennBench: a benchmark suite for embedded Java (2002) (26)
An arithmetic unit for on-line computation. (1977) (25)
Compiler-directed high-level energy estimation and optimization (2005) (25)
A micro-grained VLSI signal processor (1992) (25)
Energy savings through compression in embedded Java environments (2002) (25)
A Fast and Simple Steiner Routing Heuristic (1999) (25)
The design of a register renaming unit (1999) (24)
Memory system energy: Influence of hardware-software optimizations (2000) (24)
Impact of NBTI on FPGAs (2007) (24)
Hierarchical Soft Error Estimation Tool (HSEET) (2008) (23)
A Digit Pipelined Dynamic Time Warp Processor (1986) (23)
Databus charge recovery: practical considerations (1999) (23)
Influence of leakage reduction techniques on delay/leakage uncertainty (2005) (22)
On-line algorithms for the design of pipeline architectures (1979) (22)
On-chip Bus Thermal Analysis and Optimization (2006) (22)
Efficiently computing communication complexity for multilevel logic synthesis (1992) (22)
LAP: Loop-Block Aware Inclusion Properties for Energy-Efficient Asymmetric Last Level Caches (2016) (22)
A comparative study of power efficient SRAM designs (2000) (21)
On the application of phase relationships to complex structures. XIV. The additional use of statistical information in tangent‐formula refinement (1978) (21)
Computer vision on the MGAP (1993) (20)
An efficient architecture for motion estimation and compensation in the transform domain (2006) (20)
Multiple access caches: Energy implications (2000) (20)
Formulation and validation of an energy dissipation model for the clock generation circuitry and distribution networks (2001) (20)
Compiler-directed selective data protection against soft errors (2005) (20)
Estimating influence of data layout optimizations on SDRAM energy consumption (2003) (20)
An Overview of the Penn State Design System (1987) (20)
Characterizing dynamic and leakage power behavior in flip-flops (2002) (19)
Minimizing power consumption of static CMOS circuits by transistor sizing and input reordering (1995) (19)
Courteous cache sharing: Being nice to others in capacity management (2012) (19)
On load latency in low-power caches (2003) (19)
Experiments with a performance driven module generator (1992) (19)
Effect of compiler optimizations on memory energy (2000) (19)
Multi-level on-chip memory hierarchy design for embedded chip multiprocessors (2006) (18)
High-throughput and low-power DSP using clocked-CMOS circuitry (1995) (18)
A case for digit serial VLSI signal processors (1990) (18)
Using dynamic branch behavior for power-efficient instruction fetch (2003) (18)
Customized on-chip memories for embedded chip multiprocessors (2005) (18)
Data compression for improving SPM behavior (2004) (17)
A digit pipelined dynamic time warp processor [word recognition] (1988) (17)
A hybrid NoC design for cache coherence optimization for chip multiprocessors (2012) (17)
System level interconnect power modeling (1998) (17)
Reducing instruction cache energy consumption using a compiler-based strategy (2004) (17)
Optimizing power and performance for reliable on-chip networks (2010) (16)
Designs of emerging memory based non-volatile TCAM for Internet-of-Things (IoT) and big-data processing: A 5T2R universal cell (2016) (16)
MGAP applications in machine perception (1995) (16)
Power analysis of gated pipeline registers (1999) (16)
Use of local memory for efficient Java execution (2001) (16)
Design issues in digit serial signal processors (1989) (16)
Low Power Design: From Soup to Nuts (2000) (16)
Area Time Trade-Offs in Micro-Grain VLSI Array Architectures (1994) (16)
Implementing a family of high performance, micrograined architectures (1992) (15)
Design of a nanosensor array architecture (2004) (15)
An integer linear programming-based tool for wireless sensor networks (2005) (14)
A new optimization driven clustering algorithm for large circuits (1993) (14)
Link Shutdown Opportunities During Collective Communications in 3-D Torus Nets (2007) (14)
Impact of technology scaling and packaging on dynamic voltage scaling techniques (2002) (14)
Analyzing energy behavior of spatial access methods for memory-resident data (2001) (14)
Exploiting frequent field values in java objects for reducing heap memory requirements (2005) (14)
Clock network and phase-locked loop power estimation and experimentation (2002) (14)
A Parallel ASIC Architecture for Efficient Fractal Image Coding (1998) (14)
A complete phase-locked loop power consumption model (2002) (14)
Enhancing L2 organization for CMPs with a center cell (2006) (14)
Adaptive Garbage Collection for Battery-Operated Environments (2002) (14)
A pipelined processing unit for on-line division (1978) (14)
Multi-Level Logic Synthesis Using Communication Complexity (1989) (13)
Analyzing data reuse for cache reconfiguration (2005) (13)
Energy-aware code cache management for memory-constrained Java devices (2003) (13)
Memory system energy (poster session): influence of hardware-software optimizations (2000) (13)
Fully Digit On-Line Networks (1983) (13)
Fast Methods for Switch-Level Verification of MOS Circuits (1987) (13)
Influence of array allocation mechanisms on memory system energy (2001) (13)
Exploring heterogeneous NoC design space (2011) (13)
Phase-aware adaptive hardware selection for power-efficient scientific computations (2007) (13)
Mesh Arrays and Logician: A Tool for Their Efficient Generation (1987) (13)
An FPGA-based accelerator for cortical object classification (2012) (13)
An analytical power estimation model for crossbar interconnects (2002) (13)
A two-dimensional, distributed logic processor for machine vision (1990) (13)
Inverse discrete cosine transform architecture exploiting sparseness and symmetry properties (2004) (13)
Memory Energy Management Using Software and Hardware Directed Power Mode Control (2000) (12)
EECache: Exploiting design choices in energy-efficient last-level caches for chip multiprocessors (2014) (12)
A Holistic Approach to System Level Energy Optimization (2000) (12)
Compiler-directed proactive power management for networks (2005) (12)
Energy-performance trade-offs for spatial access methods on memory-resident data (2002) (12)
A Comparison of Four Two-Dimensional Gate Matrix Layout Tools (1989) (12)
Experimental Evaluation of Energy Behavior of Iteration Space Tiling (2000) (12)
Increasing on-chip memory space utilization for embedded chip multiprocessors through data compression (2005) (11)
An Efficient Systolic Architecture For Qmf Filter Bank Trees (1992) (11)
Edge detection using fine-grained parallelism in VLSI (1993) (11)
Power and performance comparison of crossbars and buses as on-chip interconnect structures (1999) (11)
Performance, energy, and reliability tradeoffs in replicating hot cache lines (2003) (11)
Load Miss Prediction - Exploiting Power Performance Trade-offs (2007) (11)
Conjugate gradient sparse solvers: performance-power characteristics (2006) (11)
The design of the MGAP-2: a micro-grained massively parallel array (2000) (11)
Compiler-directed cache polymorphism (2002) (11)
Energy issues in multimedia systems (1999) (10)
Evaluating alternative implementations for LDPC decoder check node function (2004) (10)
Unifying carry-sum and signed-digital number representations for low power (1995) (10)
Reducing dynamic and leakage energy in VLIW architectures (2006) (10)
Being Stingy with Multipliers (1990) (10)
REEact: a customizable virtual execution manager for multicore platforms (2012) (10)
Variation-Aware Low-Power Buffer Design (2007) (10)
Energy-aware compilation and execution in Java-enabled mobile devices (2003) (10)
Low power tradeoffs in signal processing hardware primitives (1994) (10)
Designing energy-efficient software (2002) (10)
Power-efficient trace caches (2002) (9)
Power-Area Trade-Offs in Divided Word Line Memory Arrays (1997) (9)
Variation Analysis of CAM Cells (2007) (9)
VLIW scheduling for energy and performance (2001) (9)
Impact of process scaling on the efficacy of leakage reduction schemes (2004) (9)
Design of energy-efficient circuits and systems using tunnel field effect transistors (2013) (9)
A parallel, general purpose CAM architecture (1986) (9)
Energy-efficient Java execution using local memory and object co-location (2004) (9)
Digit systolic algorithms for fine-grain architectures (1993) (9)
Digit pipelined discrete wavelet transform (1994) (9)
Networks on Chip (NoC): Interconnects of Next Generation Systems on Chip (2005) (9)
Analyzing heap error behavior in embedded JVM environments (2004) (8)
System level power analysis (1996) (8)
A framework for energy estimation of VLIW architecture (2001) (8)
Total Power Optimization for Combinational Logic Using Genetic Algorithms (2010) (8)
Using Data Compression for Increasing Memory System Utilization (2009) (8)
Adapting application execution in CMPs using helper threads (2009) (8)
Managing Leakage Energy in Cache Hierarchies (2003) (8)
Power-efficient implementation of turbo decoder in SDR system (2004) (8)
Number representations for reducing switched capacitance in subband coding (1998) (8)
Evaluating the impact of architectural-level optimizations on clock power (2001) (8)
Design of databus charge recovery mechanism (2000) (8)
A fast algorithm for minimizing the Elmore delay to identified critical sinks (1997) (8)
Adapting Application Mapping to Systematic Within-Die Process Variations on Chip Multiprocessors (2008) (8)
Neutron-induced soft error rate measurements in semiconductor memories (2007) (8)
SESEE: A soft error simulation and estimation engine (2004) (8)
Masking the energy behaviour of encryption algorithms (2003) (8)
Multi-way FSM decomposition based on interconnect complexity (1993) (8)
CCC: crossbar connected caches for reducing energy consumption of on-chip multiprocessors (2003) (8)
An architectural design for parallel fractal compression (1996) (7)
Reducing dTLB energy through dynamic resizing (2003) (7)
Proceedings of the 36th annual ACM/IEEE Design Automation Conference (1999) (7)
Effect of Power Optimizations on Soft Error Rate (2003) (7)
Predictive Precharging for Bitline Leakage Energy Reduction (2002) (7)
A Unified Energy Estimation Framework with Integrated Hardware-Software Optimizations (2000) (7)
The MGAP-2: an advanced, massively parallel VLSI signal processor (1995) (7)
Field level analysis for heap space optimization in embedded java environments (2004) (7)
DECOMPOSER: a synthesizer for systolic systems (1988) (7)
Reconfigurable Pipeline Systems (1978) (7)
Evaluating the role of scratchpad memories in chip multiprocessors for sparse matrix computations (2008) (7)
VLSI Architectures for the (1995) (7)
Energy-Aware Instruction Scheduling (2000) (7)
Architectural optimizations for a floating point multiply-accumulate unit in a graphics pipeline (1996) (7)
Ring data location prediction scheme for Non-Uniform Cache Architectures (2008) (7)
VL-CDRAM: variable line sized cached DRAMs (2003) (7)
Address Register Assignment for Reducing Code Size (2003) (7)
The arithmetic cube II: a second generation VLSI DSP processor (1991) (6)
Building high performance signal processors cheaply and quickly (1993) (6)
Analysis and solutions to issue queue process variation (2008) (6)
Reliability Aware Performance and Power Optimization in DVFS-Based On-Chip Networks (2010) (6)
Block-based frequency scalable technique for efficient hierarchical coding (2006) (6)
The MGAP's programming environment and the *C++ language (1995) (6)
An architecture for motion estimation in the transform domain (2004) (6)
Reducing code size through address register assignment (2006) (6)
Energy-efficient instruction cache using page-based placement (2001) (6)
Proceedings of the 2001 International Symposium on Low Power Electronics and Design, 2001, Huntington Beach, California, USA, 2001 (2001) (6)
High Level Specification and Synthesis of Sequential Logic Modules (1991) (6)
Number representations for reducing data bus power dissipation (1998) (6)
Distortion processing in image matching problems (1990) (6)
2-D discrete cosine transforms on a fine grain array processor (1994) (6)
SoC design skills: collaboration builds a stronger SoC design team (2001) (5)
Techniques for Designing Energy-Aware MPSoCs (2005) (5)
Reducing the number of counters needed for integer multiplication (1995) (5)
Low power circuit techniques for fast carry-skip adders (1996) (5)
Energy and performance considerations in work partitioning for mobile spatial queries (2003) (5)
Scheduling reusable instructions for power reduction (2004) (5)
Three dimensional graphics algorithms on the Micro-Grain Array Processor. II (1997) (5)
Reshaping cache misses to improve row-buffer locality in multicore systems (2013) (5)
On improving performance and energy profiles of sparse scientific applications (2006) (5)
Morphable Cache Architectures: Potential Benefits (2001) (5)
A rational arithmetic processor (1981) (5)
Digit Serial Multipliers (1991) (5)
Object duplication for improving reliability (2006) (5)
SPARTA: Simulation of Physics on a Real-Time Architecture (2000) (5)
Soft errors in adder circuits (2004) (5)
A System for Designing, Simulating, and Testing High Performance VLSI Signal Processors (1986) (5)
Energy-delay analysis for on-chip interconnect at the system level (1999) (5)
Symmetric encryption in reconfigurable and custom hardware (2005) (5)
Energy/performance modeling for collective communication in 3-D torus cluster networks (2006) (5)
Investigating Simple Low Latency Reliable Multiported Register Files (2007) (5)
Implementation and evaluation of a migration-based NUCA design for chip multiprocessors (2008) (5)
Towards Energy-Aware Iteration Space Tiling (2000) (5)
Tracking object life cycle for leakage energy optimization (2003) (5)
Tuning data replication for improving behavior of MPSoC applications (2004) (5)
EECache: A Comprehensive Study on the Architectural Design for Energy-Efficient Last-Level Caches in Chip Multiprocessors (2015) (5)
Optimizing Leakage Energy Consumption in Cache Bitlines (2004) (5)
Evolving the ACM journal distribution program (2007) (5)
Hardware/software co-design for real-time physical modeling (2000) (5)
The Arithmetic Cube: error analysis and simulation (1991) (4)
Leakage-aware interconnect for on-chip network (2005) (4)
Ring Prediction for Non-Uniform Cache Architectures (2007) (4)
A unified energy framework with integrated hardware-software optimizations (2000) (4)
Exploiting bank locality in multi-bank memories (2003) (4)
Motion Analysis on the Micro Grained Array Processor (1997) (4)
Exploiting value locality for secure-energy aware communication (2003) (4)
Memory energy characterization and optimization for the SPEC2000 benchmarks (2001) (4)
The power analysis of interconnect structures (1997) (4)
Predictive precharging for bitline leakage energy reduction [microprocessor caches] (2002) (4)
Optimising power efficiency in trace cache fetch unit (2007) (4)
Input sensitive high-level power analysis (2001) (4)
Compiler directed network-on-chip reliability enhancement for chip multiprocessors (2010) (4)
A clock power model to evaluate impact of architectural and technology optimizations - a summary (2003) (4)
Design considerations for databus charge recovery (2001) (4)
A Fault-Handling Methodology by Promoting Hardware Configurations via PageRank (2011) (4)
Exploring performance-power tradeoffs in providing reliability for NoC-based MPSoCs (2011) (4)
Using data compression in an MPSoC architecture for improving performance (2005) (4)
Leveraging Emerging Technology Through Architectural Exploration for the Routing Fabric of Future FPGAs (2011) (4)
Temperature and Voltage Scaling Effects on Electrical Masking (4)
Architectural-level power estimation and experimentation (2000) (4)
A Real Time Embedded Face Detector on FPGA (2006) (4)
SimplePower : A Cycle-Accurate Energy Simulator (2000) (4)
A comparison of two digit serial VLSI adders (1988) (4)
BB-GC: basic-block level garbage collection (2005) (4)
Low power considerations in the design of pipelined FIR filters (1995) (4)
Design tradeoffs in high speed multipliers and FIR filters (1996) (4)
A nanosensor array-based VLSI gas discriminator (2005) (4)
Efficient VLSI implementation of inverse discrete cosine transform [image coding applications] (2004) (4)
Power consumption and performance comparative study of logarithmic-time CMOS adders (2000) (4)
A Massively Parallel, Micro-grained VLSI Architecture (1993) (4)
Input recoding for reducing power in distributed arithmetic (1998) (4)
Distributed Fault Diagnosis in the Butterfly Parallel Processor (1989) (4)
Test generation in circuits constructed by input decomposition (1990) (3)
Aggressive Dynamic Execution of Decoded Traces (1997) (3)
Leakage-aware compilation for VLIW architectures (2005) (3)
Modeling energy of the clock generation and distribution circuitry (2000) (3)
The substrate noise detector for noise tolerant mixed-signal IC (2003) (3)
FPGA-based synthesis of FSMs through decomposition (1994) (3)
Digit pipelined arithmetic on fine-grain array processors (1995) (3)
FUNCTIONAL VERIFICATION OF DIGITAL MOS CIRCUITS. (1986) (3)
Secretary/Treasurer's Report (1997) (3)
Architectural level hierarchical power estimation of control units (1998) (3)
Dynamic circuit synthesis using the Owens tool set (1998) (3)
High performance array processor for video decoding (2005) (3)
Implementing algorithms for convolution on arrays of adders (1989) (3)
Using Data Compression to Increase Energy Savings in Multi-bank Memories (2004) (3)
The MGAP: a high performance, user programmable, multifunctional architecture for DSP (1994) (3)
Design tradeoffs in CMOS FIR filters (1996) (3)
Adaptive software for scientific computing: co-managing quality-performance-power tradeoffs (2005) (3)
Fast algorithm for performance-oriented Steiner routing (1995) (3)
Polynomial Time Testability of Circuits Generated by Input Decomposition (1994) (3)
Online pipeline systems for recursive numeric computations (1980) (3)
Influence of MPEG-4 parameters on system energy (2002) (2)
The design and implementation of the Arithmetic Cube II, a VLSI signal processing system (1993) (2)
Dswitch : Write-aware Dynamic Inclusion Property Switching for Emerging Asymmetric Memory Technologies (2016) (2)
Mapping high-dimension wavefront computations to silicon (1990) (2)
Multidimensional algorithms for VLSI processors (1988) (2)
Code protection for resource-constrained embedded devices (2004) (2)
Memory Optimizations For Fast Power-Aware Sparse Computations (2007) (2)
Designing leakage aware multipliers (2004) (2)
Special Issue on Parallelism in Computer Arithmetic (1988) (2)
Traffic steering between a low-latency unswitched TL ring and a high-throughput switched on-chip interconnect (2013) (2)
Characterizing the Performance and Energy Attributes of Scientific Simulations (2006) (2)
Digit serial systolic VLSI architectures (1990) (2)
Synthesis of Multi-level Reed Muller Circuits Using Matrix Transformations (1993) (2)
Re-evaluating MPEG motion compensation search criteria (1998) (2)
A simulation methodology for software energy evaluation (1997) (2)
Intermediate-level vision tasks on a memory array architecture (1993) (2)
Reducing non-deterministic loads in low-power caches via early cache set resolution (2007) (2)
Low power design for systems on a chip (1999) (2)
A systolic VLSI architecture for multi-dimensional transforms (1993) (2)
Integrated code and data placement in two-dimensional mesh based chip multiprocessors (2008) (2)
Investigating Memory System Energy Behavior Using Software and Hardware Optimizations (2001) (2)
Characterization of memory energy behavior (2001) (2)
On-Chip Memory Management for Embedded MpSoC Architectures Based on Data Compression (2005) (2)
T-NUCA - a novel approach to non-uniform access latency cache architectures for 3D CMPs (2010) (2)
Power characterization of functional units (1999) (2)
Proceedings of the 2006 ACM SIGPLAN/SIGBED conference on Language, compilers, and tool support for embedded systems (2006) (2)
Dynamic space warping algorithms on fine-grain array processors (1994) (2)
A memory array architecture for computer vision (1989) (2)
Shared caches in multicores: the good, the bad, and the ugly (2010) (2)
On the Effects of Process Variation (2010) (2)
Power and area reduction using carbon nanotube bundle interconnect in global clock tree distribution network (2009) (2)
Introducing MGAP-2 [Micro-Grain Array Processor] (1995) (2)
The MGAP-2: a micro-grained massively parallel array processor (1995) (2)
A clocked, static circuit technique for building efficient high frequency pipelines (1997) (2)
In-Network Caching for Chip Multiprocessors (2008) (2)
Masking the Energy Behavior of Encryption Algorithms (2003) (2)
Image processing on a memory array architecture (1991) (2)
Logic synthesis for programmable logic devices (1990) (2)
Activity Clustering for Leakage Management in SPMs (2006) (1)
PERFLEX: a performance driven module generator (1992) (1)
Soft error modeling and analysis of the Neutron Intercepting Silicon Chip (NISC) (2011) (1)
Energy-aware hardware and software optimizations for embedded systems (2003) (1)
Lower bound study on interconnect complexity of the decomposed finite state machines (1995) (1)
An optimal time multiplication free algorithm for edge detection on a mesh (1996) (1)
Editorial (2005) (1)
Architectural-level power estimation for system-on-a-chip (1999) (1)
Cosmic ray background effects on the neutron intercepting silicon chip (NISC) (2011) (1)
Computation and transmission energy modeling through profiling for MPEG4 video transmission (2003) (1)
Testing neutron-induced soft errors in semiconductor memory, invited (2004) (1)
TESTING NEUTRON-INDUCED SOFT ERRORS IN SEMICONDUCTOR MEMORIES Participants: (2007) (1)
Toward a power efficient computer architecture for Barnes-Hut N-body simulations (2006) (1)
Reduction of broadband noise in speech by spectral weighting (1980) (1)
Computing: report leaps geographical barriers but stumbles over gender (2006) (1)
Tree Cache – A Novel Approach to Non-Uniform Access Latency Cache Architectures for 3 D CMPs (2009) (1)
Proceedings of the 2002 International Symposium on Low Power Electronics and Design, 2002, Monterey, California, USA, August 12-14, 2002 (2002) (1)
A module generator for high performance CMOS circuits (1992) (1)
ON THE BUILDING OF A PACKET SWITCHED NETWORK OF MICROCOMPUTERS. (1980) (1)
Adaptive Burst-Writes (ABW) (2015) (1)
A high level synthesis tool for systolic designs (1988) (1)
Energy and timing characterization of VLSI charge-pump phase-locked loops (2003) (1)
Hardware-software co-adaptation for data-intensive embedded applications (2002) (1)
Reducing Energy Consumption in Chip Multiprocessors Using Workload Variations (2004) (1)
The MGAP family of processor arrays (1997) (1)
Proceedings : 11th Symposium on Computer Arithmetic, June 29-July 2, 1993, Windsor, Ontario (1993) (1)
Motion estimation algorithms on fine grain array processors (1995) (1)
Aggressive dynamic execution of multimedia kernel traces (1998) (1)
Power efficient adaptive M-QAM design using adaptive pipelined analog-to-digital converter (2002) (1)
SOFT ERRORS: MODELING AND INTERACTIONS WITH POWER OPTIMIZATIONS (2005) (1)
Hardware and software techniques for DRAM energy management (2001) (1)
EECache (2015) (1)
Parallel uses for serial arithmetic in signal processors (1991) (1)
Platform-aware dynamic configuration support for efficient text processing on heterogeneous system (2015) (1)
A new IIR algorithm based on the overlap-save approach (1997) (1)
Area Time Trade-offs in Micro-Grain (1994) (1)
Exploiting temporal loads for low latency and high bandwidth memory (2005) (1)
Issues in high performance multimedia (2000) (1)
Dynamic core partitioning for energy efficiency (2010) (1)
Recent developments in performance driven Steiner routing: an overview (1996) (0)
Designing energy-efficient and reliable caches and interconnects (2005) (0)
Mixed-autonomy local interconnect for reconfigurable SIMD arrays (1997) (0)
11th Symposium on Computer Arithmetic, 29 June - 2 July 1993, Windsor, Canada, Proceedings (1993) (0)
EFFECTOFCOMPILEROPTIMIZATIONS ON MEMORY ENERGY (2000) (0)
Hotspot Avoidance Through Runtime Reconfiguration in Network-On-Chip Designs (2004) (0)
Small signal model for low power DSP (1995) (0)
A simulation methodology for evaluating parallel computers (1995) (0)
Rapid prototyping with programmable control paths (1994) (0)
Improved Security in Multi AESTHETIC Processor using AES Architecture (2020) (0)
Numerical limitations on the design of digit online networks (1983) (0)
Designing reliable circuit in the presence of soft errors (2005) (0)
Editorial Message (1998) (0)
Power-Aware Designers at Odds with Power Grid Designers? (2003) (0)
- Compiler-Directed Communication Energy Optimizations for Microsensor Networks (2012) (0)
Building high speed, energy-efficient cmos circuits using variations in circuits techniques (1996) (0)
Power, delay and area tradeoff in cmos arithmetic modules (1996) (0)
Tools and Techniques for Integrated Hardware-Software Energy Optimizations (2002) (0)
Using Memory Compression for Energy Reduction in an Embedded Java System (2002) (0)
TaPEr: tackling power emergencies in the dark silicon era by exploiting resource scalability (2015) (0)
Video compression and image analysis on a fine-grained array processor (1996) (0)
Total power optimization through simultaneously multiple-V/sub DD/ multiple-V/sub TH/ assignment and device sizing with stack forcing (2004) (0)
Aggressive Dynamic Execution of Multimedia (1998) (0)
Thermal neutron induced soft error rate measurement in semiconductor memories and circuits (2008) (0)
A fast compact addition architecture for low power microprocessors and DSP chips (1996) (0)
Design of fast pipelined arithmetic units in VLSI (2013) (0)
A new blocked IIR algorithm (1993) (0)
Arithmetic systems for low-power signal processing (1998) (0)
X-REEact: Fighting Runtime Variances across Time and Space (2012) (0)
Analyzing heap error behavior in embedded JVM environments (2004) (0)
A rapid turn-around system for designing efficient fine grained signal processors (1989) (0)
On the testability of cascaded Reed Muller circuits (1993) (0)
An integrated, multi-level synthesis system (1990) (0)
Energy Optimization Using Object Co-Location in Java (2007) (0)
On-chip memory space partitioning for chip multiprocessors using polyhedral algebra (2010) (0)
Tota I Power 0 pt i m izat i o n t h rough Si mu Ita neous I y Multiple-V,, Multiple-V,, Assignment and Device Sizing with Stack Forcing (2004) (0)
Designing Energy-Aware Sensor Systems (2012) (0)
Power Reduction Techniques in the Processor Core (1999) (0)
Session details: Microarchitecural techniques for power reduction (2004) (0)
Proceedings of the 2006 ACM SIGPLAN/SIGBED Conference on Languages, Compilers, and Tools for Embedded Systems (LCTES'06), Ottawa, Ontario, Canada, June 14-16, 2006 (2006) (0)
Circuits and systems society VLSI transactions best paper award-2003 (2003) (0)
Special Issue Short Papers Transistor Sizing for Low Power CMOS Circuits (1996) (0)
An Energy-Aware Approach for Sensor Data Communication (2012) (0)
Proceedings of the 2004 International Conference on Compilers, Architecture, and Synthesis for Embedded Systems, CASES 2004, Washington DC, USA, September 22 - 25, 2004 (2004) (0)
Rapid prototyping of signal processors in an educational environment (1995) (0)
Proceedings of the 14th International Conference on Architectural Support for Programming Languages and Operating Systems, ASPLOS 2009, Washington, DC, USA, March 7-11, 2009 (2009) (0)
Testing Neutron-induced Soft Errors (2007) (0)
Managing power, performance and reliability trade-offs (2008) (0)
Techniques for high speed and low power cmos circuit design (1996) (0)
Logic Synthesis for Multi-level Reed Muller Circuits Using Matrix Transformations (1993) (0)
Analyzing software influences on substrate noise: an ADC perspective (2004) (0)
ECube: An Efficient Architecture for Analyzing Time-Varying Spectra (1992) (0)
On-chip interconnect power modeling and optimization (1999) (0)
An efficient implementation of hierarchical image coding (2003) (0)
Session details: Microarchitecture-level power analysis and optimization techniques (2005) (0)
Signal Processing Algorithms for Heterogeneous Architectures (1993) (0)
Proceedings of the 14th international conference on Architectural support for programming languages and operating systems (2009) (0)
Fine-grain instruction scheduling for low energy (2002) (0)
Technology scaling redirects main memories (2010) (0)
Design and implementation of real time video processor (1986) (0)
Technical Perspective Technology Scaling Redirects Main Memories (2010) (0)
Introduction to the Special Issue on Computer Arithmetic (1994) (0)
A robust CMOS logic technique for building high frequency circuits with efficient pipelining (1997) (0)
An Exploration of Hardware Architectures for Face Detection (2006) (0)
Towards Minimizing the Adverse Effects of Temperature on High Performance Digital Systems (2010) (0)
Expanded VLSI Architectures. (1984) (0)
Soft error rate measurements in semiconductor memories at Pennsylvania state university (2007) (0)
A digit online arithmetic simulator (1982) (0)
Proceedings : 8th Symposium on Computer Arithmetic, May 19-21, 1987, Villa Olmo, Como, Italy (1987) (0)
Exploring the Possibility of Operating in the Compressed Domain (2004) (0)
Steven P. Levitan (1950-2016) (2016) (0)
Digit pipelined processors (1987) (0)

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