Matteo Sonza Reorda

Matteo Sonza Reorda's AcademicInfluence.com Rankings

Matteo Sonza Reorda

Engineering

#6807

World Rank

#8152

Historical Rank

Electrical Engineering

#2071

World Rank

#2176

Historical Rank

Applied Physics

#2246

World Rank

#2285

Historical Rank

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Engineering

Why Is Matteo Sonza Reorda Influential?

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According to Wikipedia, Matteo Sonza Reorda is an electrical engineer at the Politecnico di Torino, Italy. He was named a Fellow of the Institute of Electrical and Electronics Engineers in 2016 for his design of test algorithms for reliable circuits and systems. Actually he is the head of CAD - Electronic CAD & Reliabillity Group at Politecnico di Torino. He teaches Computer architectures.

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Matteo Sonza Reorda's Published Works

Number of citations in a given year to any of this author's works

Total number of citations to an author for the works they published in a given year. This highlights publication of the most important work(s) by the author

Published Works

RT-Level ITC'99 Benchmarks and First ATPG Results (2000) (483)
On the optimal design of triple modular redundancy logic for SRAM-based FPGAs (2005) (249)
Soft-error detection using control flow assertions (2003) (246)
Microprocessor Software-Based Self-Testing (2010) (239)
Soft-error detection through software fault-tolerance techniques (1999) (166)
Software-Implemented Hardware Fault Tolerance (2010) (159)
Low power BIST via non-linear hybrid cellular automata (2000) (149)
Automatic test program generation: a case study (2004) (138)
GATTO: a genetic algorithm for automatic test pattern generation for large synchronous sequential circuits (1996) (122)
A source-to-source compiler for generating dependable software (2001) (106)
An FPGA-Based Approach for Speeding-Up Fault Injection Campaigns on Safety-Critical Circuits (2002) (105)
Experimentally evaluating an automatic approach for generating safety-critical software with respect to transient errors (2000) (105)
Evaluating the effects of SEUs affecting the configuration memory of an SRAM-based FPGA (2004) (102)
Fully automatic test program generation for microprocessor cores (2003) (98)
A diagnostic test pattern generation algorithm (1990) (98)
A test pattern generation methodology for low power consumption (1998) (97)
An automatic test pattern generator for large sequential circuits based on Genetic Algorithms (1994) (90)
Simulation-based analysis of SEU effects in SRAM-based FPGAs (2002) (90)
Exploiting circuit emulation for fast hardness evaluation (2001) (87)
On the test of microprocessor IP cores (2001) (85)
New techniques for speeding-up fault-injection campaigns (2002) (84)
A new hybrid fault detection technique for systems-on-a-chip (2006) (80)
Using Benchmarks for Radiation Testing of Microprocessors and FPGAs (2015) (76)
An accurate analysis of the effects of soft errors in the instruction and data caches of a pipelined microprocessor (2003) (73)
Testability analysis and ATPG on behavioral RT-level VHDL (1997) (72)
GALLO: a genetic algorithm for floorplan area optimization (1996) (71)
GPGPUs: How to combine high computational power with high reliability (2014) (66)
On the evaluation of SEU sensitiveness in SRAM-based FPGAs (2004) (66)
Fast sequential circuit test generation using high-level and gate-level techniques (1998) (62)
Exploiting FPGA-based techniques for fault injection campaigns on VLSI circuits (2001) (59)
A new BIST architecture for low power circuits (1999) (59)
The selfish gene algorithm: a new evolutionary optimization strategy (1998) (58)
New techniques for accelerating fault injection in VHDL descriptions (2000) (57)
Diagnosis oriented test pattern generation (1990) (55)
Exploiting FPGA for accelerating fault injection experiments (2001) (55)
New static compaction techniques of test sequences for sequential circuits (1997) (54)
Industrial BIST of embedded RAMs (1995) (52)
Advanced techniques for GA-based sequential ATPGs (1996) (51)
Automatic test program generation for pipelined processors (2003) (47)
A new software-based technique for low-cost fault-tolerant application (2003) (44)
Multiple errors produced by single upsets in FPGA configuration memory: a possible solution (2005) (44)
Fault behavior observation of a microprocessor system through a VHDL simulation-based fault injection experiment (1996) (44)
GARDA: a diagnostic ATPG for large synchronous sequential circuits (1995) (43)
A New Approach to Software-Implemented Fault Tolerance (2004) (43)
High-level and hierarchical test sequence generation (2002) (42)
An RT-level fault model with high gate level correlation (2000) (42)
Automatic test bench generation for validation of RT-level descriptions: an industrial experience (2000) (42)
Exploiting programmable bist for the diagnosis of embedded memory cores (2003) (41)
A suite of IEEE 1687 benchmark networks (2016) (39)
Coping with SEUs/SETs in microprocessors by means of low-cost solutions: a comparison study (2001) (38)
Hardware and Software Transparency in the Protection of Programs Against SEUs and SETs (2008) (38)
A Flexible Framework for the Automatic Generation of SBST Programs (2016) (37)
Software-Based Hardening Strategies for Neutron Sensitive FFT Algorithms on GPUs (2014) (36)
A software fault tolerance method for safety-critical systems: effectiveness and drawbacks (2002) (35)
Test Program Generation for Communication Peripherals in Processor-Based SoC Devices (2009) (35)
A new functional fault model for FPGA application-oriented testing (2002) (34)
An Effective Technique for Minimizing the Cost of Processor Software-Based Diagnosis in SoCs (2006) (34)
Improved software-based processor control-flow errors detection technique (2005) (32)
Analysis of SEU effects in a pipelined processor (2002) (32)
Evaluating the fault tolerance capabilities of embedded systems via BDM (1999) (31)
A Low-Cost Solution for Deploying Processor Cores in Harsh Environments (2011) (31)
EXFI: a low-cost fault injection system for embedded microprocessor-based boards (1998) (31)
Behavioral-level test vector generation for system-on-chip designs (2000) (31)
A new evolutionary algorithm inspired by the selfish gene theory (1998) (30)
High-level observability for effective high-level ATPG (2000) (30)
Accurate and efficient analysis of single event transients in VLSI circuits (2003) (30)
On-line functionally untestable fault identification in embedded processor cores (2013) (30)
On the Functional Test of Branch Prediction Units (2011) (29)
On-line software-based self-test of the Address Calculation Unit in RISC processors (2012) (29)
An Effective Technique for the Automatic Generation of Diagnosis-Oriented Programs for Processor Cores (2008) (29)
On the testability of IEEE 1687 networks (2015) (28)
On the transformation of manufacturing test sets into on-line test sets for microprocessors (2005) (27)
Effective techniques for high-level ATPG (2001) (27)
An error-detection and self-repairing method for dynamically and partially reconfigurable systems (2017) (27)
FPGA-based fault injection for microprocessor systems (2001) (27)
An industrial environment for high-level fault-tolerant structures insertion and validation (2002) (27)
System-in-package testing: problems and solutions (2006) (26)
Using infrastructure IPs to support SW-based self-test of processor cores (2004) (26)
Impact of data cache memory on the single event upset-induced error rate of microprocessors (2003) (26)
FlexGripPlus: An improved GPGPU model to support reliability analysis (2020) (26)
Hybrid Genetic Algorithms for the Travelling Salesman Problem (1993) (26)
A Functional Power Evaluation Flow for Defining Test Power Limits during At-Speed Delay Testing (2011) (25)
A programmable BIST for DRAM testing and diagnosis (2010) (25)
Evolutionary test program induction for microprocessor design verification (2002) (24)
Embedded Memory Diagnosis: An Industrial Workflow (2006) (24)
Exploring the impact of functional test programs re-used for power-aware testing (2015) (24)
An effective approach to automatic functional processor test generation for small-delay faults (2014) (23)
A new SBST algorithm for testing the register file of VLIW processors (2012) (23)
Hybrid soft error detection by means of infrastructure IP cores [SoC implementation] (2004) (23)
A new model for improving symbolic product machine traversal (1992) (23)
A low-cost SEE mitigation solution for soft-processors embedded in Systems on Pogrammable Chips (2009) (23)
An on-line fault detection technique based on embedded debug features (2010) (22)
On the in-field functional testing of decode units in pipelined RISC processors (2014) (22)
An experimental analysis of the effects of migration in parallel genetic algorithms (1993) (22)
Early evaluation of bus interconnects dependability for system-on-chip designs (2001) (22)
On the use of embedded debug features for permanent and transient fault resilience in microprocessors (2012) (22)
A pattern ordering algorithm for reducing the size of fault dictionaries (2006) (22)
Cellular automata for deterministic sequential test pattern generation (1997) (21)
Comparing topological, symbolic and GA-based ATPGs: an experimental approach (1996) (21)
Evaluating Different Solutions to Design Fault Tolerant Systems with SRAM-based FPGAs (2007) (21)
Integrating BIST techniques for on-line SoC testing (2005) (21)
On the automatic generation of SBST test programs for in-field test (2015) (21)
A Hybrid Approach to the Test of Cache Memory Controllers Embedded in SoCs (2008) (21)
Efficient estimation of SEU effects in SRAM-based FPGAs (2005) (21)
On the automation of the test flow of complex SoCs (2006) (21)
RoRA: a reliability-oriented place and route algorithm for SRAM-based FPGAs (2005) (21)
Code Generation for Functional Validation of Pipelined Microprocessors (2003) (20)
Efficient machine-code test-program induction (2002) (20)
An integrated HW and SW fault injection environment for real-time systems (1998) (20)
On the evaluation of soft-errors detection techniques for GPGPUs (2013) (19)
MIHST: A Hardware Technique for Embedded Microprocessor Functional On-Line Self-Test (2014) (19)
Making the circular self-test path technique effective for real circuits (1994) (19)
Using symbolic techniques to find the maximum clique in very large sparse graphs (1995) (19)
On-line analysis and perturbation of CAN networks (2004) (18)
On the Functional Test of the Register Forwarding and Pipeline Interlocking Unit in Pipelined Processors (2013) (18)
Optimal vector selection for low power BIST (1999) (18)
Evaluating the effects of transient faults on vehicle dynamic performance in automotive systems (2004) (18)
A Novel SBST Generation Technique for Path-Delay Faults in Microprocessors Exploiting Gate- and RT-Level Descriptions (2008) (18)
Efficient Techniques for Automatic Verification-Oriented Test Set Optimization (2006) (18)
Improving topological ATPG with symbolic techniques (1995) (17)
Reliability analysis reloaded: How will we survive? (2013) (17)
A fault injection environment for microprocessor-based boards (1998) (17)
Scan insertion criteria for low design impact (1996) (17)
RT-level Fault Simulation Techniques based on Simulation Command Scripts (2000) (17)
On the Automatic Generation of Optimized Software-Based Self-Test Programs for VLIW Processors (2014) (17)
Accurate dependability analysis of CAN-based networked systems (2003) (17)
Evolving Cellular Automata for Self-Testing Hardware (2000) (17)
On-line detection of control-flow errors in SoCs by means of an infrastructure IP core (2005) (17)
Automatic test bench generation for simulation-based validation (2000) (17)
A Hybrid Approach for Detection and Correction of Transient Faults in SoCs (2010) (17)
Online Test of Control Flow Errors: A New Debug Interface-Based Approach (2016) (16)
Initializability analysis of synchronous sequential circuits (2002) (16)
Low Power BIST via Hybrid Cellular Automata (2000) (16)
A genetic algorithm for floorplan area optimization (1994) (16)
Evaluating system dependability in a co-design framework (2000) (16)
An Error-Detection and Self-Repairing Method for Dynamically and Partially Reconfigurable Systems (2013) (16)
A New Hybrid Nonintrusive Error-Detection Technique Using Dual Control-Flow Monitoring (2014) (16)
Optimizing deceptive functions with the SG-Clans algorithm (1999) (16)
Identification and Rejuvenation of NBTI-Critical Logic Paths in Nanoscale Circuits (2016) (15)
New techniques for efficiently assessing reliability of SOCs (2003) (15)
Automatic test programs generation driven by internal performance counters (2004) (15)
Fault Injection-based Reliability Evaluation of SoPCs (2006) (15)
On test program compaction (2015) (15)
Testing permanent faults in pipeline registers of GPGPUs: A multi-kernel approach (2019) (15)
About the functional test of the GPGPU scheduler (2018) (15)
A P1500 compliant BIST-based approach to embedded RAM diagnosis (2001) (15)
A genetic algorithm for automatic generation of test logic for digital circuits (1996) (15)
Software-level soft-error mitigation techniques (2011) (14)
Circular Self-Test Path for FSMs (1996) (14)
An extended model to support detailed GPGPU reliability analysis (2019) (14)
An approach to sequential circuit diagnosis based on formal verification techniques (1992) (14)
Exploiting an I-IP for in-field SoC test (2004) (14)
A simulation-based approach to test pattern generation for synchronous sequential circuits (1992) (14)
Early, accurate dependability analysis of CAN-based networked systems (2006) (14)
A genetic algorithm-based system for generating test programs for microprocessor IP cores (2000) (14)
Test of Reconfigurable Modules in Scan Networks (2018) (14)
New Techniques to Reduce the Execution Time of Functional Test Programs (2017) (14)
Exploiting the Selfish Gene algorithm for evolving hardware cellular automata (2000) (14)
Effectiveness and limitations of various software techniques for "soft error" detection: a comparative study (2001) (13)
System safety through automatic high-level code transformations: an experimental evaluation (2001) (13)
An Automated Methodology for Cogeneration of Test Blocks for Peripheral Cores (2007) (13)
Multi-level Fault Effects Evaluation (2007) (13)
Coping with SEUs/SETs in microprocessors by means of low-cost solutions: a comparative study and experimental results (2001) (13)
Evaluating Alpha-induced soft errors in embedded microprocessors (2009) (13)
A data parallel algorithm for Boolean function manipulation (1995) (13)
Software-based self-test of embedded microprocessors (2011) (13)
A P1500-compatible programmable BIST approach for the test of embedded flash memories (2003) (13)
Testing logic cores using a BIST P1500 compliant approach: a case of study (2005) (12)
FPGA-Based Fault Injection Techniques for Fast Evaluation of Fault Tolerance in VLSI Circuits (2001) (12)
Evaluating the effectiveness of a software fault-tolerance technique on RISC- and CISC-based architectures (2000) (12)
Online hardening of programs against SEUs and SETs (2006) (12)
On the functional test of Branch Prediction Units based on Branch History Table (2011) (12)
A Low-Cost Reliability vs. Cost Trade-Off Methodology to Selectively Harden Logic Circuits (2017) (12)
Analyzing SEU effects is SRAM-based FPGAsb (2003) (12)
Test Program Generation from High-level Microprocessor Descriptions (2005) (12)
On-line Testing of an Off-the-shelf Microprocessor Board for Safety-critical Applications (1996) (12)
FlexFi: A Flexible Fault Injection Environment for Microprocessor-Based Systems (1999) (12)
Optimizing area loss in flat glass cutting (1997) (12)
Automatic generation of stimuli for fault diagnosis in IEEE 1687 networks (2016) (12)
Fault Grading Techniques of Software Test Libraries for Safety-Critical Applications (2019) (11)
A SBST strategy to test microprocessors' Branch Target Buffer (2012) (11)
System-level Test and Validation of Hardware/Software Systems (2005) (11)
Exploiting the selfish gene algorithm for evolving cellular automata (2000) (11)
An analysis of test solutions for COTS-based systems in space applications (2018) (11)
Dependability analysis of CAN networks: an emulation-based approach (2003) (11)
About on-line functionally untestable fault identification in microprocessor cores for safety-critical applications (2018) (11)
VEGA: a verification tool based on genetic algorithms (1998) (11)
Fault list compaction through static timing analysis for efficient fault injection experiments (2002) (11)
Integrating Online and Offline Testing of a Switching Memory (1998) (11)
Exploring the Mysteries of System-Level Test (2020) (11)
Random testability analysis: comparing and evaluating existing approaches (1988) (11)
An enhanced FPGA-based low-cost tester platform exploiting effective test data compression for SoCs (2009) (11)
A portable ATPG tool for parallel and distributed systems (1995) (11)
A low-cost programmable board for speeding-up fault injection in microprocessor-based systems (1999) (11)
An Exact and Efficient Critical Path Tracing Algorithm (2010) (11)
A new approach to cope with single event upsets in processor-based systems (2006) (10)
Hardware-accelerated path-delay fault grading of functional test programs for processor-based systems (2007) (10)
Test Time Minimization in Reconfigurable Scan Networks (2016) (10)
High Quality System Level Test and Diagnosis (2014) (10)
A Parallel Genetic Algorithm for Automatic Generation of Test Sequences for Digital Circuits (1996) (10)
Boolean Function Manipulation on a Parallel System Using BDDs (1997) (10)
Advanced technologies for transient faults detection and compensation (2011) (10)
Boolean function manipulation on massively parallel computers (1992) (10)
On the Automatic Generation of Test Programs for Path-Delay Faults in Microprocessor Cores (2007) (9)
Evolving effective CA/CSTP: BIST architectures for sequential circuits (2001) (9)
On Reducing the Peak Power Consumption of Test Sequences (1999) (9)
A new approach for initialization sequences computation for synchronous sequential circuits (1997) (9)
Exploiting Competing Subpopulations for Automatic Generation of Test Sequences for Digital Cicuits (1996) (9)
A Hybrid Fault-Tolerant Architecture for Highly Reliable Processing Cores (2016) (9)
Optimized embedded memory diagnosis (2011) (9)
Software-Based Testing for System Peripherals (2012) (9)
Efficient analysis of single event transients (2004) (9)
A Parallel Tester Architecture for Accelerometer and Gyroscope MEMS Calibration and Test (2011) (9)
On the development of Software-Based Self-Test methods for VLIW processors (2012) (9)
Exploiting the debug interface to support on-line test of control flow errors (2013) (9)
An experimental evaluation of the effectiveness of automatic rule-based transformations for safety-critical applications (2000) (9)
Experiences in the use of evolutionary techniques for testing digital circuits (1998) (8)
Evaluating the Impact of DfM Library Optimizations on Alpha-induced SEU Sensitivity in a Microprocessor Core (2009) (8)
A Deterministic Methodology for Identifying Functionally Untestable Path-Delay Faults in Microprocessor Cores (2008) (8)
High-level test generation for hardware testing and software validation (2003) (8)
Control flow checking through embedded debug interface (2011) (8)
Effective Screening of Automotive SoCs by Combining Burn-In and System Level Test (2019) (8)
Floorplan area optimization using genetic algorithms (1994) (8)
Revealing GPUs Vulnerabilities by Combining Register-Transfer and Software-Level Fault Injection (2021) (8)
A low-cost SEE mitigation solution for soft-processors embedded in systems on programmable chips (2009) (8)
Simulation-based sequential equivalence checking of RTL VHDL (1999) (8)
An efficient fault simulation technique for transition faults in non-scan sequential circuits (2009) (8)
Detailed comparison of dependability analyses performed at RT and gate levels (2003) (8)
Automatic Generation of Test Sets for SBST of Microprocessor IP Cores (2005) (8)
A New Architecture to Cross-Fertilize On-Line and Manufacturing Testing (2011) (8)
Exploiting symbolic techniques for partial scan flip flop selection (1998) (8)
Partial scan flip flop selection for simulation-based sequential ATPGs (1996) (8)
Software-Based Self-Test Strategy for Data Cache Memories Embedded in SoCs (2008) (8)
On the functional test of the cache coherency logic in multi-core systems (2015) (8)
A software-based self-test methodology for system peripherals (2010) (8)
On the Generation of Functional Test Programs for the Cache Replacement Logic (2009) (8)
Assessing the diagnostic power of test pattern sets (1990) (8)
An Efficient Method for the Test of Embedded Memory Cores during the Operational Phase (2013) (8)
Automatic generation of validation stimuli for application-specific processors (2004) (8)
Generating power-hungry test programs for power-aware validation of pipelined processors (2010) (8)
Observability solutions for in-field functional test of processor-based systems (2015) (8)
CA-CSTP: a new BIST architecture for sequential circuits (2000) (8)
An experimental comparison of different approaches to ROM BIST (1991) (8)
An automatic approach to perform the verification of hardware designs according to the ISO26262 functional safety standard (2017) (8)
New evolutionary techniques for test-program generation for complex microprocessor cores (2005) (7)
Improved techniques for multiple stuck-at fault analysis using single stuck-at fault test sets (1992) (7)
An Evolutionary Technique for Reducing the Duration of Reconfigurable Scan Network Test (2018) (7)
Validation of the dependability of CAN-based networked systems (2004) (7)
On the identification of optimal cellular automata for built-in self-test of sequential circuits (1998) (7)
On the functional test of the BTB logic in pipelined and superscalar processors (2013) (7)
Accurate Analysis of Single Event Upsets in a Pipelined Microprocessor (2003) (7)
Microprocessor Testing: Functional Meets Structural Test (2017) (7)
A New Technique to Generate Test Sequences for Reconfigurable Scan Networks (2018) (7)
Enhancing topological ATPG with high-level information and symbolic techniques (1998) (7)
Automatic Functional Stress Pattern Generation for SoC Reliability Characterization (2009) (7)
Automatic test generation for verifying microprocessors (2005) (7)
Increasing fault coverage during functional test in the operational phase (2013) (7)
An effective methodology for on-line testing of embedded microprocessors (2011) (7)
Exploiting an I-IP for both Test and Silicon Debug of Microprocessor Cores (2005) (7)
Speeding-Up Fault Injection Campaigns in VHDL Models (2000) (7)
A Hybrid Approach to Fault Detection and Correction in SoCs (2007) (7)
An On-Line Testing Technique for the Scheduler Memory of a GPGPU (2020) (7)
A tester architecture suitable for MEMS calibration and testing (2010) (7)
A Functional Approach for Testing the Reorder Buffer Memory (2014) (7)
Design space exploration and optimization of a Hybrid Fault-Tolerant Architecture (2015) (7)
Cellular Automata for Sequent ial Test Pattern Generation (1997) (7)
Symbat''s user guide (1993) (6)
A High-Level Approach to Analyze the Effects of Soft Errors on Lossless Compression Algorithms (2017) (6)
Implementing a safe embedded computing system in SRAM-based FPGAs using IP cores: A case study based on the Altera NIOS-II soft processor (2011) (6)
Effective generation and evaluation of diagnostic SBST programs (2016) (6)
Built-In Self Test (2009) (6)
High Quality Test Pattern Generation for RT-level VHDL Descriptions (1999) (6)
Optimization of Self Checking FIR filters by means of Fault Injection Analysis (2007) (6)
A functional test algorithm for the register forwarding and pipeline interlocking unit in pipelined microprocessors (2013) (6)
On the optimized generation of Software-Based Self-Test programs for VLIW processors (2012) (6)
Fault Injection for Embedded Microprocessor-based Systems (1999) (6)
An industrial experience in the built-in self test of embedded RAMs (1994) (6)
A dynamic reconfiguration mechanism to increase the reliability of GPGPUs (2020) (6)
Combining Architectural Simulation and Software Fault Injection for a Fast and Accurate CNNs Reliability Evaluation on GPUs (2021) (6)
Fast Power Evaluation for Effective Generation of Test Programs Maximizing Peak Power Consumption (2013) (6)
A P1500 compliant architecture for BIST-based Diagnosis of embedded RAMs (2001) (6)
An Enhanced Strategy for Functional Stress Pattern Generation for System-on-Chip Reliability Characterization (2010) (6)
Assessing Test Procedure Effectiveness for Power Devices (2018) (6)
In-field Functional Test of CAN Bus Controllers (2020) (6)
DfT Reuse for Low-Cost Radiation Testing of SoCs: A Case Study (2009) (6)
A New Approach to the Analysis of Single Event Transients in VLSI Circuits (2004) (6)
Hardening of serial communication protocols for potentially critical systems in automotive applications: LIN bus (2013) (6)
An improved data parallel algorithm for Boolean function manipulation using BDDs (1995) (6)
SymFony: a hybrid topological-symbolic ATPG exploiting RT-level information (1999) (6)
Fast differential fault simulation by dynamic fault ordering (1991) (6)
An effective approach for functional test programs compaction (2016) (6)
Neutron sensitivity and hardening strategies for Fast Fourier Transform on GPUs (2013) (6)
Software-Based Self-Test for Transition Faults: a Case Study (2019) (6)
Exploiting MOEA to Automatically Geneate Test Programs for Path-Delay Faults in Microprocessors (2008) (6)
Fault injection analysis of transient faults in clustered VLIW processors (2011) (6)
SW-based transparent in-field memory testing (2015) (6)
High-reliability fault tolerant digital systems in nanometric technologies: Characterization and design methodologies (2012) (5)
On the on-line functional test of the Reorder Buffer memory in superscalar processors (2013) (5)
A software-based methodology for the generation of peripheral test sets based on high-level descriptions (2007) (5)
Automatic test program generation from RT-level microprocessor descriptions (2002) (5)
System-Level Test: State of the Art and Challenges (2021) (5)
Evaluating the radiation sensitivity of GPGPU caches: New algorithms and experimental results (2014) (5)
Challenges of Reliability Assessment and Enhancement in Autonomous Systems (2019) (5)
A genetic algorithm for the computation of initialization sequences for synchronous sequential circuits (1997) (5)
Hardware-in-the-loop-based dependability analysis of automotive systems (2006) (5)
Approximate equivalence verification of sequential circuits via genetic algorithms (1999) (5)
Fault-Independent Test-Generation for Software-Based Self-Testing (2019) (5)
A BIST-based Solution for the Diagnosis of Embedded Memories Adopting Image Processing Techniques (2002) (5)
A new solution to on-line detection of Control Flow Errors (2014) (5)
Scan-Chain Intra-Cell Aware Testing (2018) (5)
Evaluating Data Encryption Effects on the Resilience of an Artificial Neural Network (2020) (5)
On the functional test of L2 caches (2012) (5)
On the Modeling of Gate Delay Faults by Means of Transition Delay Faults (2011) (5)
Proving finite state machines correct with an automaton-based method (1991) (5)
Industrial Track paper On-line Testing of an Off-the-shelf Microprocessor Board for Safety- critical Applications ~ (1996) (5)
Improving the Functional Test Delay Fault Coverage: A Microprocessor Case Study (2016) (5)
A multi-level approach to the dependability analysis of networked systems based on the CAN protocol (2004) (5)
An Interpretation Framework for Evaluating High-Level Fault Models and ATPG Capabilities (2001) (5)
Increasing the Fault Coverage of Processor Devices during the Operational Phase Functional Test (2014) (5)
On the in-field test of the GPGPU scheduler memory (2019) (5)
GA‐Based Verification of Network Protocols Performance (2000) (5)
A dynamic hardware redundancy mechanism for the in-field fault detection in cores of GPGPUs (2020) (5)
Reliability Assessment of Neural Networks in GPUs: A Framework For Permanent Faults Injections (2022) (5)
Finding the Maximurn Clique in a Graph Using BDDs (1993) (5)
Untestable faults identification in GPGPUs for safety-critical applications (2019) (5)
On the evaluation of SEU effects in GPGPUs (2019) (5)
Testing a switching memory in a telecommunication system (1995) (5)
Functional test generation for DMA controllers (2010) (5)
A New Fault Injection Approach for Testing Network-on-Chips (2012) (5)
An integrated approach for increasing the soft-error detection capabilities in SoCs processors (2005) (5)
Multilevel Simulation Methodology for FMECA Study Applied to a Complex Cyber-Physical System (2020) (5)
Emulation-Based Analysis of Soft Errors in Deep Sub-micron Circuits (2003) (5)
Rejuvenation of nanoscale logic at NBTI-critical paths using evolutionary TPG (2015) (5)
Validation and robustness assessment of an automotive system (2013) (5)
An novel Methodology for Reducing SoC Test Data Volume on FPGA-based Testers (2008) (5)
A new approach to build a low-level malicious fault list starting from high-level description and alternative graphs (1997) (4)
A Compaction Method for STLs for GPU in-field test (2022) (4)
A simulation-based approach to test pattern generation for synchronous circuits (1992) (4)
Effective Diagnostic Pattern Generation Strategy for Transition-Delay Faults in Full-Scan SOCs (2009) (4)
Analysis of the effects of soft errors on compression algorithms through fault injection inside program variables (2016) (4)
Peak Power Estimation: A Case Study on CPU Cores (2012) (4)
An Enhanced Technique for the Automatic Generation of Effective Diagnosis-oriented Test Programs for Processor (2007) (4)
Assessing the Effectiveness of the Test of Power Devices at the Board Level (2019) (4)
An Evolutionary Methodology to Enhance Processor Software-Based Diagnosis (2006) (4)
Cumulative embedded memory failure bitmap display & analysis (2010) (4)
Exploiting an infrastructure-intellectual property for systems-on-chip test, diagnosis and silicon debug (2010) (4)
Design validation of multithreaded architectures using concurrent threads evolution (2009) (4)
Determined-Safe Faults Identification: A step towards ISO26262 hardware compliant designs (2020) (4)
ARPIA: A High-Level Evolutionary Test Signal Generator (2001) (4)
Faults Detection in the Heatsinks Mounted on Power Electronic Transistors (2020) (4)
Early reliability evaluation of a biomédical system (2014) (4)
On the detection of board delay faults through the execution of functional programs (2017) (4)
Hybrid symbolic-explicit techniques for the graph coloring problem (1997) (4)
Fault-Tolerance Techniques for Soft-Core Processors Using the Trace Interface (2016) (4)
An On-board Data-Handling Computer for Deep-Space Exploration Built Using Commercial-Off-the-Shelf SRAM-Based FPGAs (2009) (4)
On the robustness of DCT-based compression algorithms for space applications (2016) (4)
SAARA: a simulated annealing algorithm for test pattern generation for digital circuits (1997) (4)
Interactive presentation: An enhanced technique for the automatic generation of effective diagnosis-oriented test programs for processor (2007) (4)
Automated test program reordering for efficient SBST (2017) (4)
Functional test generation for the pLRU replacement mechanism of embedded cache memories (2011) (4)
A new algorithm for diagnosis-oriented automatic test pattern generation (1990) (4)
The General Product Machine: a New Model for Symbolic FSM Traversal (1998) (4)
A novel scalable and reconfigurable emulation platform for embedded systems verification (2010) (4)
Software-Based On-Line Test of Communication Peripherals in Processor-Based Systems for Automotive Applications (2006) (4)
Improving GPU register file reliability with a comprehensive ISA extension (2020) (4)
Guaranteeing testability in re-encoding for low power (1997) (4)
Exploiting an infrastructure IP to reduce memory diagnosis costs in SoCs (2005) (4)
Reducing test application time through interleaved scan (2002) (4)
Applicative System Level Test introduction to Increase Confidence on Screening Quality (2020) (4)
Self Checking Circuit Optimization by means of Fault Injection Analysis: A Case Study on Reed Solomon Decoders (2007) (4)
Rejuvenation of NBTI-Impacted Processors Using Evolutionary Generation of Assembler Programs (2016) (4)
System-level test bench generation in a co-design framework (2000) (4)
Test-Plan Optimization for Flying-Probes In-Circuit Testers (2019) (3)
Exact probabilistic testability measures for multi-output circuits (1990) (3)
ALPS: a peak power estimation tool for sequential circuits (1999) (3)
Analyzing the Sensitivity of GPU Pipeline Registers to Single Events Upsets (2020) (3)
On the diagnostic analysis of IEEE 1687 networks (2016) (3)
Effective SAT-based Solutions for Generating Functional Sequences Maximizing the Sustained Switching Activity in a Pipelined Processor (2021) (3)
Evolutionary Simulation-Based Validation (2004) (3)
New categories of Safe Faults in a processor-based Embedded System (2019) (3)
Report on benchmark identification and planning of experiments to be performed (2002) (3)
Automotive Microcontroller End-of-Line Test via Software-Based Methodologies (2007) (3)
Special session 8B — Panel: In-field testing of SoC devices: Which solutions by which players? (2014) (3)
Exploiting logic simulation to improve simulation-based sequential ATPG (1997) (3)
A Novel Sequence Generation Approach to Diagnose Faults in Reconfigurable Scan Networks (2020) (3)
A low-cost susceptibility analysis methodology to selectively harden logic circuits (2016) (3)
The Product Machine and Implicit Enumeration to prove FSMs correct (1991) (3)
Fault-Independent Test-Generation for Software-Based Self-Testing (2018) (3)
An Effective Approach for the Diagnosis of Transition-Delay Faults in SoCs, based on SBST and Scan Chains (2007) (3)
Improved Test Solutions for COTS-Based Systems in Space Applications (2018) (3)
TPDL: Extended temporal profile description language (1991) (3)
FPGA-controlled PCBA power-on self-test using processor's debug features (2016) (3)
On the test of a COTS-based system for space applications (2018) (3)
Special Session: AutoSoC - A Suite of Open-Source Automotive SoC Benchmarks (2020) (3)
Hybrid soft error mitigation techniques for COTS processor-based systems (2016) (3)
On the in-field test of Branch Prediction Units using the correlated predictor mechanism (2014) (3)
On the in-field test of embedded memories (2017) (3)
An efficient algorithm for the extraction of compressed diagnostic information from embedded memory cores (2003) (3)
Hardening the software with respect to transient errors: a method and experimental results (2000) (3)
A data parallel approach to Boolean function manipulation using BDDs (1994) (3)
Evaluating Software-based Hardening Techniques for General-Purpose Registers on a GPGPU (2020) (3)
The training environment for the course on microprocessor systems at the Politecnico di Torino (1998) (3)
On Test Program Generation for Peripheral Components in a SoC Resorting to High-Level Metrics (2007) (3)
Comparing ATPGs for synchronous sequential circuits (1991) (3)
Transformation-based peak power reduction for test sequences (1999) (3)
Approximate Equivalence Verification for Protocol Interface Implementation via Genetic Algorithms (1999) (3)
GATTO: an intelligent tool for automatic test pattern generation for digital circuits (1994) (3)
On the development of diagnostic test programs for VLIW processors (2013) (3)
A parallel system for test pattern generation (1991) (3)
The Use of Benchmarks for High-Reliability Systems (2015) (2)
Functional Verification of DMA Controllers (2011) (2)
Model Checking and Graph Theory in Sequential ATPG (1990) (2)
An improved cellular automata-based BIST architecture for sequential circuits (2000) (2)
Introducing SW-based fault handling mechanisms to cope with EMI in embedded electronics: are they a good remedy? (2003) (2)
Automatic Completion and Refinement of Verification Sets for Microprocessor Cores (2005) (2)
On the maximization of the sustained switching activity in a processor (2015) (2)
A Low-Cost Emulation System for Fast Co-verification and Debug (2011) (2)
TORSIM: An efficient fault simulator for synchronous sequential circuits (1994) (2)
A Semi-Formal Technique to Generate Effective Test Sequences for Reconfigurable Scan Networks (2018) (2)
A BIST-based solution for the diagnosis of embedded memories adopting image processing techniques (2002) (2)
Assessing the Effectiveness of Different Test Approaches for Power Devices in a PCB (2021) (2)
Testing Heatsink Faults in Power Transistors by means of Thermal Model (2020) (2)
A BDD Package For A Massively Parallel SIMD Architecture (1994) (2)
Test, Reliability and Functional Safety Trends for Automotive System-on-Chip (2022) (2)
Simulation-based verification of network protocols performance (1997) (2)
A programmable BIST approach for the diagnosis of embedded memory cores (2003) (2)
On the Functional Test of Special Function Units in GPUs (2021) (2)
A New Evolutionary Paradigm for Cultivating Cellular Automata for Built-In Self Test of Sequential Circuits (2002) (2)
On the Design of a Fault Tolerant Ripple-Carry Adder with Controllable-Polarity Transistors (2015) (2)
A non-intrusive on-line control flow error detection technique for SoCs (2007) (2)
A novel SEU injection setup for Automotive SoC (2022) (2)
Exploiting high-level descriptions for circuits fault tolerance assessments (1997) (2)
BASTION: Board and SoC test instrumentation for ageing and no failure found (2017) (2)
Towards Making Fault Injection on Abstract Models a More Accurate Tool for Predicting RT-Level Effects (2017) (2)
Analysis of the equivalences and dominances of transient faults at the RT level (2002) (2)
An optimized hybrid approach to provide fault detection and correction in SoCs (2007) (2)
An experimental analysis of the effectiveness of the circular self-test path technique (1994) (2)
Self-Test Libraries Analysis for Pipelined Processors Transition Fault Coverage Improvement (2021) (2)
Permanent faults on LIN networks: On-line test generation (2014) (2)
A PVM tool for automatic test generation on parallel and distributed systems (1995) (2)
A Dynamic Greedy Test Scheduler for Optimizing Probe Motion in In-Circuit Testers (2019) (2)
In-field test of safety-critical systems: is functional test a feasible solution? (2015) (2)
Innovative methods for Burn-In related Stress Metrics Computation (2021) (2)
A System-layer Infrastructure for SoC Diagnosis (2007) (2)
Permanent fault detection and diagnosis in the lightweight dual modular redundancy architecture (2015) (2)
Scan-chain intra-cell defects grading (2015) (2)
Exploiting embedded FPGA in on-line software-based test strategies for microprocessor cores (2009) (2)
The Use of Model Checking in ATPG for Sequential Circuits (1990) (2)
An extended GPGPU model to support detailed reliability analysis (2020) (2)
An Effective Method to Identify Microarchitectural Vulnerabilities in GPUs (2022) (2)
On the optimization of SBST test program compaction (2017) (2)
Enhanced Observability in Microprocessor-based Systems for Permanent and Transient Fault Resiliency (2010) (2)
An FPGA-Emulation-Based Platform for Characterization of Digital Baseband Communication Systems (2011) (2)
Testable Synthesis of Control Units via Circular Self-Test Path: Problems and Solutions (1996) (2)
Evaluating the Code Encryption Effects on Memory Fault Resilience (2020) (2)
Testability measures with concurrent good simulation (1989) (2)
Exploiting the background debugging mode in a fault injection system (1998) (2)
Using Parallel Genetic Algorithms for Solving the Min-Cut Problem (1996) (2)
On the testing of special memories in GPGPUs (2020) (2)
RESCUE: Cross-Sectoral PhD Training Concept for Interdependent Reliability, Security and Quality (2018) (1)
VLSI-SoC: Opportunities and Challenges Beyond the Internet of Things (2017) (1)
Recovery scheme for hardening system on programmable chips (2009) (1)
Observability solutions for infield functional test of processor-based systems : a survey and quantitative test case evaluation (2016) (1)
An Infrastructure IP for Soft Error Detection (2004) (1)
A Cellular Genetic Algorithm for the Floorplan Area Optimization Problem on a SIMD Architecture (1996) (1)
Towards the Integration of Reliability and Security Mechanisms to Enhance the Fault Resilience of Neural Networks (2021) (1)
New Techniques for the Automatic Identification of Uncontrollable Lines in a CPU Core (2021) (1)
An open source embedded-GPGPU model for the accurate analysis and mitigation of SEU effects (2019) (1)
Exploiting symbolic techniques within genetic algorithms for power optimization (1997) (1)
A hierarchical approach for designing dependable systems (2002) (1)
Automatic Validation of Protocol Interfaces Described in VHDL (2000) (1)
Exact probabilistic testability measures for multi-output circuits (1990) (1)
An Enhanced Evolutionary Technique for the Generation of Compact Reconfigurable Scan-Network Tests (2019) (1)
Fault tolerant and BIST design of a FIFO cell (1996) (1)
Fault injection in GPGPU cores to validate and debug robust parallel applications (2014) (1)
Expressing logical and temporal conditions in simulation environments: TPDL* (1989) (1)
Comparing different solutions for testing resistive defects in low-power SRAMs (2021) (1)
Verifying Reliability (Dagstuhl Seminar 12341) (2012) (1)
A new technique to check the correct mounting of the power module heatsinks (2022) (1)
Diagnosing Faulty Functional Units in Processors by Using Automatically Generated Test Sets (2005) (1)
Test Solution for Heatsinks in Power Electronics Applications (2020) (1)
About Performance Faults in Microprocessor Core in-field Testing (2019) (1)
On the Automatic Generation of Software-Based Self-Test Programs for Functional Test and Diagnosis of VLIW Processors (2012) (1)
Coupling different methodologies to validate obsolete microprocessors (2004) (1)
Protecting GPU's Microarchitectural Vulnerabilities via Effective Selective Hardening (2021) (1)
An evolutionary algorithm for reducing integrated-circuit test application time (2002) (1)
Software-Based Self-Test for Delay Faults (2019) (1)
Self-checking and fault tolerant approaches can help BIST fault coverage: a case study (1996) (1)
A new DFM-proactive technique (2005) (1)
A Multi-level Approach to Evaluate the Impact of GPU Permanent Faults on CNN's Reliability (2022) (1)
A New Methodology for Debugging Embedded Cores (2002) (1)
Cross-fertilizing FSM verification techniques and sequential diagnosis (1992) (1)
RESCUE EDA Toolset for Interdependent Aspects of Reliability, Security and Quality in Nanoelectronic Systems Design (2019) (1)
New Perspectives on Core In-field Path Delay Test (2020) (1)
An RT-level concurrent error detection technique for data dominated systems (2003) (1)
Built-In Self Test of Sequential Circuits (2003) (1)
Testing the Divergence Stack Memory on GPGPUs: A Modular in-Field Test Strategy (2020) (1)
On the generation of test programs for chip multi-thread computer architectures (2008) (1)
E-Learning at Politecnico di Torino: Moving to a Sustainable Large-Scale Multi-Channel System of Services (2012) (1)
Design and Verification of an open-source SFU model for GPGPUs (2020) (1)
Modular Functional Testing: Targeting the Small Embedded Memories in GPUs (2020) (1)
Soft error effects analysis and mitigation in VLIW safety-critical applications (2014) (1)
A Fault Injection Environment for SoPC's Embedded Microprocessors (2006) (1)
DYRE: a DYnamic REconfigurable solution to increase GPGPU’s reliability (2021) (1)
On Automatic Test Block Generation for Peripheral Testing in SoCs via Dynamic FSMs Extraction (2007) (0)
Efficient verification of sequential circuits on a parallel system (1992) (0)
About the functional test of permanent faults in distributed systems (2015) (0)
A High-Level Approach to Analyze the Effects of Soft Errors on Lossless Compression Algorithms (2017) (0)
Neural Network's Reliability to Permanent Faults: Analyzing the Impact of Performance Optimizations in GPUs (2022) (0)
Welcome note from the technical program chairs (2017) (0)
Evolutionary Algorithms for Low Power Test Pattern Generator (2016) (0)
Test Generation: A Heuristic Approach (2005) (0)
STLs for GPUs: Using High-Level Language Approaches (2023) (0)
Guest Editor's Introduction: Special Section on High Dependability Systems (2020) (0)
Effective techniques for automatically improving the transition delay fault coverage of Self-Test Libraries (2022) (0)
On-line test of embedded systems: Which role for functional test? (2012) (0)
Recent Trends and Perspectives on Defect-Oriented Testing (2022) (0)
Exploiting post-silicon debug hardware to improve the fault coverage of Software Test Libraries (2022) (0)
An effective ATPG flow for Gate Delay Faults (2015) (0)
Early Power Estimation for System-on-Chip Designs (2000) (0)
Using Hardware Performance Counters to support infield GPU Testing (2021) (0)
Automating the Generation of Programs Maximizing the Repeatable Constant Switching Activity in Microprocessor Units via MaxSAT (2023) (0)
Guest Editors' Introduction: SBCCI 2019 (2021) (0)
Probabilistic Testability Analysis (1989) (0)
High-level ATPG: a real topic or an academic amusement? (1999) (0)
A hardware accelerated framework for the generation of design validation programs for SMT processors (2010) (0)
Final Report on Project Results (2000) (0)
Approaching production diagnostic for BIST-based testing (2004) (0)
REFU: Redundant Execution with Idle Functional Units, Fault Tolerant GPGPU architecture (2022) (0)
Evaluating the Impact of Transition Delay Faults in GPUs (2023) (0)
An Automatic Functional Stress Pattern Generation Technique Suitable for SoC Reliability Characterization (2008) (0)
Devising an RT-Level ATPG for uProcessor Cores (2001) (0)
Partition-Based Faults Diagnosis of a VLIW Processor (2013) (0)
A Systematic Method to Generate Effective STLs for the In-Field Test of CAN Bus Controllers (2022) (0)
FAULT TOLERANT DIGITAL SYSTEMS DESIGN 01LHUIU (Presentation of the course) (2003) (0)
Evaluating low-level software-based hardening techniques for configurable GPU architectures (2022) (0)
Test generation and coverage metrics (2009) (0)
Proceedings of the 9th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2006), Prague, Czech Republic, April 18-21, 2006 (2006) (0)
Maximizing the Switching Activity of Different Modules Within a Processor Core via Evolutionary Techniques (2021) (0)
Evaluating the impact of DFM library optimizations on alpha-induced SEU sensitivity in a microprocessor core (2009) (0)
Parallel processing analysis of the 1-D KPZ growth equation (1994) (0)
Effective fault simulation of GPU’s permanent faults for reliability estimation of CNNs (2022) (0)
A transputer-based gate-level fault simulator (1990) (0)
Selected Peer-Reviewed Articles from the 14th IEEE Latin-American Test Workshop, Cordoba, Argentina, April 3-5, 2013 (2014) (0)
Using Formal Methods to Support the Development of STLs for GPUs (2022) (0)
A novel Pattern Selection Algorithm to reduce the Test Cost of large Automotive Systems-on-Chip (2022) (0)
A Low-Cost Burn-In Tester Architecture to Supply Effective Electrical Stress (2023) (0)
Automating the Generation of Programs Maximizing the Sustained Switching Activity in Microprocessor units via Evolutionary Techniques (2023) (0)
Evolutionary Techniques for Minimizing Test Signals Application Time (2002) (0)
Automatic Test Program Generation — a Case Study: the SPARC V8 (2003) (0)
Machine Learning for Test, Diagnosis, Post-Silicon Validation and Yield Optimization (2022) (0)
Preprint High Quality System Level Test and Diagnosis (2014) (0)
AN EFFICIENT METHODOLOGY FOR REDUCING SoC TEST DATA VOLUME ON LOW-COST TESTERS (2008) (0)
Guest Editorial (2004) (0)
Analysis of the Equivalences and Dominances of Transient Faults at the Register-Transfer Level (2002) (0)
Software-Based Testing for System Peripherals (2012) (0)
A Hybrid Fault Injection Methodology for Real Time Systems (1998) (0)
Analysis of root causes of alpha sensitivity variations on microprocessors manufactured using different cell layouts (2010) (0)
Massively Extended Modular Monitoring and a Second Life for Upper Stages (2018) (0)
Evaluation of methodologies for the estimation of power consumption in integrated digital systems (2019) (0)
Design techniques to improve the resilience of computing systems: software layer (2020) (0)
Extended Fault Detection Techniques for Systems-on-Chip (2007) (0)
Automated Identification of Application-Dependent Safe Faults in Automotive Systems-on-a-Chips (2022) (0)
Improving the Fault Resilience of Neural Network Applications Through Security Mechanisms (2022) (0)
In-field Data Collection System through Logic BIST for large Automotive Systems-on-Chip (2022) (0)
A Hybrid Fault-Tolerant Architecture for Highly Reliable Processing Cores (2016) (0)
A Functional Approach for Testing the Reorder Buffer Memory (2014) (0)
A New Method to Generate Software Test Libraries for In-Field GPU Testing Resorting to High-Level Languages (2022) (0)
Towards an automatic approach for hardware verification according to ISO 26262 functional safety standard (2018) (0)
New Acceleration Techniques for Simulation-Based Fault-Injection (2003) (0)
Automatic Verification of RT-Level Microprocessor Cores Using Behavioral Specifications: a Case Study (2004) (0)
Characterizing a Neutron-Induced Fault Model for Deep Neural Networks (2022) (0)
Using STLs for Effective In-Field Test of GPUs (2023) (0)
An Optimized Burn-In Stress Flow targeting Interconnections logic to Embedded Memories in Automotive Systems-on-Chip (2022) (0)
Correction to: Improved Test Solutions for COTS-Based Systems in Space Applications (2018) (0)
Role of fault injection techniques in system dependability analysis (1996) (0)
Session details: Jitter test and fault diagnosis (2008) (0)
Proceedings on 4th IEEE International On-Line Testing Workshop, July 6-8, Capri, Italy (1997) (0)
RESCUE: Interdependent Challenges of Reliability, Security and Quality in Nanoelectronic Systems (2019) (0)
Exploiting massively parallel architectures for the solution of diffusion and propagation problems (1995) (0)
Online scheduling of concurrent Memory BISTs execution at Real-Time Operating-System level (2022) (0)
Memory BIST (2008) (0)
On the diagnosis of embedded memory cores through Programmable BIST (2004) (0)
Reducing SEU sensitivity in LIN networks: Selective and collaborative hardening techniques (2014) (0)
Prediction of Power Requirements for High-Speed Circuits (2000) (0)
Test techniques for Advanced Processors (2005) (0)
26 The Reliability Challenge from Random Process Variability Induced Timing Errors (2012) (0)
A Tool for Supporting and Automating the Test of Complex System-on-Chips (2005) (0)
Exploiting massively parallel architectures for the analysis of growth phenomena (1994) (0)
Design Validation of Multithreaded Processors Using Threads Evolution (2010) (0)
Increasing the Fault Coverage of Processor Devices during the Operational Phase Functional Test (2014) (0)
A Low-Cost Reliability vs. Cost Trade-Off Methodology to Selectively Harden Logic Circuits (2017) (0)
A Simulation-based approach to Test Pattern Generation for (1992) (0)
Safety Evaluation of NanoFabrics (2007) (0)
An algebraic approach to test generation for sequential circuits (1991) (0)
BUILT-IN SELF TEST OF SEQUENTIAL CIRCUITS A New Evolutionary Paradigm for Cultivating Cellular Automata (2002) (0)
Cerberus I-IP: an HW/SW approach to Control Flow Checking (2004) (0)
A comparative overview of ATPG flows targeting traditional and cell-aware fault models (2022) (0)
Identification and Rejuvenation of NBTI-Critical Logic Paths in Nanoscale Circuits (2016) (0)
A new hardware/software platform for the soft-error sensitivity evaluation of FPGA devices (2007) (0)
GUEST EDITORIAL (2012) (0)
Integrating On-Line and Off-Line Testing of a Switching Memory in a Telecommunication System (1998) (0)
Self-Test Library Generation for In-field Test of Path Delay faults (2023) (0)
Guest Editorial (2003) (0)
IEEE European Test Symposium (ETS) (2019) (0)
Centralized vs. distributed implementation of FSM equivalence verification on a parallel system (1992) (0)
An Experimental Evaluation of Resistive Defects and Different Testing Solutions in Low-Power Back-Biased SRAM Cells (2022) (0)
Test Pattern Generation Under Low Power Constraints (1999) (0)
Software Techniques for Dependable Computer-based Systems (2004) (0)
A system for evaluating on-line testability at the RT-level (1998) (0)
A multi-level approach to the dependability analysis of CAN networks for automotive applications (2004) (0)
Microarchitectural Reliability Evaluation of a Block Scheduling Controller in GPUs (2022) (0)
An adaptive tester architecture for volume diagnosis (2010) (0)
Report on Dissemination Plan (2002) (0)
Evaluating the impact of Permanent Faults in a GPU running a Deep Neural Network (2022) (0)
An I-IP for the Debug of Microprocessor Cores (2005) (0)
Pandora I-IP: an HW/SW approach to Control Flow Checking (2005) (0)
Verifying the equivalence of sequential circuits with genetic algorithms (1999) (0)
2012 JETTA Reviewers (2013) (0)
A Novel Compaction Approach for SBST Test Programs (2021) (0)

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