Nam Sung Kim | Academic Influence

Q: What Schools Are Affiliated With Nam Sung Kim

Nam Sung Kim is affiliated with the following schools: KAIST, University of Michigan, University of Wisconsin–Madison, University of Illinois Urbana-Champaign

Why Is Nam Sung Kim Influential?

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According to Wikipedia, Nam Sung Kim is a full professor of electrical and computer engineering at the University of Illinois at Urbana–Champaign an IEEE and ACM Fellow. He was on leave for two years serving as a Corporate Senior Vice President at Samsung Electronics and leading the development of the first commercial memory product with near memory computing capability.

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Nam Sung Kim's Published Works

Number of citations in a given year to any of this author's works

Total number of citations to an author for the works they published in a given year. This highlights publication of the most important work(s) by the author

Published Works

Razor: a low-power pipeline based on circuit-level timing speculation (2003) (1395)
Leakage Current: Moore's Law Meets Static Power (2003) (1259)
Drowsy caches: simple techniques for reducing leakage power (2002) (913)
GPUWattch: enabling energy optimizations in GPGPUs (2013) (544)
Approximate Computing: A Survey (2016) (363)
Energy-Efficient and Metastability-Immune Resilient Circuits for Dynamic Variation Tolerance (2009) (354)
NDA: Near-DRAM acceleration architecture leveraging commodity DRAM devices and standard memory modules (2015) (222)
Adaptive Frequency and Biasing Techniques for Tolerance to Dynamic Temperature-Voltage Variations and Aging (2007) (222)
Circuit and microarchitectural techniques for reducing cache leakage power (2004) (201)
The case for GPGPU spatial multitasking (2012) (186)
Drowsy instruction caches. Leakage power reduction using dynamic voltage scaling and cache sub-bank prediction (2002) (174)
Energy-Efficient Approximate Multiplication for Digital Signal Processing and Classification Applications (2015) (168)
Razor: circuit-level correction of timing errors for low-power operation (2004) (141)
Chameleon: Versatile and practical near-DRAM acceleration architecture for large memory systems (2016) (100)
Wordline & Bitline Pulsing Schemes for Improving SRAM Cell Stability in Low-Vcc 65nm CMOS Designs (2006) (98)
VARIUS-NTV: A microarchitectural model to capture the increased sensitivity of manycores to process variations at near-threshold voltages (2012) (91)
Lossless and lossy memory I/O link compression for improving performance of GPGPU workloads (2012) (90)
Energy-Efficient and Metastability-Immune Timing-Error Detection and Instruction-Replay-Based Recovery Circuits for Dynamic-Variation Tolerance (2008) (83)
Optimizing throughput of power- and thermal-constrained multicore processors using DVFS and per-core power-gating (2009) (83)
Pipe-SGD: A Decentralized Pipelined SGD Framework for Distributed Deep Net Training (2018) (77)
Accurate Estimation of SRAM Dynamic Stability (2008) (77)
On-Chip Cache Device Scaling Limits and Effective Fault Repair Techniques in Future Nanoscale Technology (2007) (73)
GPU register file virtualization (2015) (73)
Improving Throughput of Power-Constrained GPUs Using Dynamic Voltage/Frequency and Core Scaling (2011) (73)
EnergySmart: Toward energy-efficient manycores for Near-Threshold Computing (2013) (71)
A Network-Centric Hardware/Algorithm Co-Design to Accelerate Distributed Training of Deep Neural Networks (2018) (66)
Reducing register ports using delayed write-back queues and operand pre-fetch (2003) (66)
Power-efficient computing for compute-intensive GPGPU applications (2012) (63)
Workload and power budget partitioning for single-chip heterogeneous processors (2012) (61)
GANAX: A Unified MIMD-SIMD Acceleration for Generative Adversarial Networks (2018) (61)
Combating Aging with the Colt Duty Cycle Equalizer (2010) (60)
Hardware Architecture and Software Stack for PIM Based on Commercial DRAM Technology : Industrial Product (2021) (57)
SleepScale: Runtime joint speed scaling and sleep states management for power efficient data centers (2014) (57)
Planaria: Dynamic Architecture Fission for Spatial Multi-Tenant Acceleration of Deep Neural Networks (2020) (55)
GradiVeQ: Vector Quantization for Bandwidth-Efficient Gradient Aggregation in Distributed CNN Training (2018) (54)
FlashShare: Punching Through Server Storage Stack from Kernel to Firmware for Ultra-Low Latency SSDs (2018) (53)
Defect Analysis and Cost-Effective Resilience Architecture for Future DRAM Devices (2017) (50)
Row-buffer decoupling: A case for low-latency DRAM microarchitecture (2014) (50)
DRAMA: An Architecture for Accelerated Processing Near Memory (2015) (49)
Coping with Parametric Variation at Near-Threshold Voltages (2013) (48)
PROMISE: An End-to-End Design of a Programmable Mixed-Signal Accelerator for Machine-Learning Algorithms (2018) (43)
FlexiGAN: An End-to-End Solution for FPGA Acceleration of Generative Adversarial Networks (2018) (43)
Minimizing total area of low-voltage SRAM arrays through joint optimization of cell size, redundancy, and ECC (2010) (42)
FlatFlash: Exploiting the Byte-Accessibility of SSDs within a Unified Memory-Storage Hierarchy (2019) (42)
CiDRA: A cache-inspired DRAM resilience architecture (2015) (41)
Challenges for architectural level power modeling (2002) (41)
QoS-aware dynamic resource allocation for spatial-multitasking GPUs (2014) (41)
COP: To compress and protect main memory (2015) (40)
Approximating warps with intra-warp operand value similarity (2016) (40)
Low-Energy Data Cache Using Sign Compression and Cache Line Bisection (2002) (37)
Application-Transparent Near-Memory Processing Architecture with Memory Channel Network (2018) (37)
A 2.3Gb/s fully integrated and synthesizable AES Rijndael core (2003) (34)
Leakage power optimization techniques for ultra deep sub-micron multi-level caches (2003) (34)
Low-Cost Per-Core Voltage Domain Support for Power-Constrained High-Performance Processors (2014) (32)
25.4 A 20nm 6GB Function-In-Memory DRAM, Based on HBM2 with a 1.2TFLOPS Programmable Computing Unit Using Bank-Level Parallelism, for Machine Learning Applications (2021) (32)
Low-voltage on-chip cache architecture using heterogeneous cell sizes for high-performance processors (2011) (32)
Energy-efficient and metastability-immune timing-error detection and recovery circuits for dynamic variation tolerance (2008) (31)
Amber*: Enabling Precise Full-System Simulation with Detailed Modeling of All SSD Resources (2018) (31)
SimpleSSD: Modeling Solid State Drives for Holistic System Simulation (2017) (30)
dist-gem5: Distributed simulation of computer clusters (2017) (30)
The microarchitecture of a low power register file (2003) (30)
Fair share: Allocation of GPU resources for both performance and fairness (2014) (29)
Optimizing total power of many-core processors considering voltage scaling limit and process variations (2009) (29)
Yield-driven near-threshold SRAM design (2007) (28)
Smart Gait-Aid Glasses for Parkinson's Disease Patients (2017) (28)
Heterogeneous Computing Meets Near-Memory Acceleration and High-Level Synthesis in the Post-Moore Era (2017) (26)
Precision-aware soft error protection for GPUs (2014) (26)
Process variation-aware workload partitioning algorithms for GPUs supporting spatial-multitasking (2014) (25)
Analyzing throughput of GPGPUs exploiting within-die core-to-core frequency variation (2011) (25)
Cost-effective power delivery to support per-core voltage domains for power-constrained processors (2012) (24)
PageForge: A Near-Memory Content-Aware Page-Merging Architecture (2017) (24)
pd-gem5: Simulation Infrastructure for Parallel/Distributed Computer Systems (2015) (24)
Reevaluating the latency claims of 3D stacked memories (2013) (23)
Analyzing Potential Throughput Improvement of Power- and Thermal-Constrained Multicore Processors by Exploiting DVFS and PCPG (2012) (21)
Collaborative (CPU + GPU) algorithms for triangle counting and truss decomposition on the Minsky architecture: Static graph challenge: Subgraph isomorphism (2017) (21)
On Effective and Efficient Quality Management for Approximate Computing (2016) (20)
Microarchitectural power modeling techniques for deep sub-micron microprocessors (2004) (20)
Memory scheduling towards high-throughput cooperative heterogeneous computing (2014) (20)
Analyzing the Impact of Joint Optimization of Cell Size, Redundancy, and ECC on Low-Voltage SRAM Array Total Area (2012) (19)
22.1 A 1.1V 16GB 640GB/s HBM2E DRAM with a Data-Bus Window-Extension Technique and a Synergetic On-Die ECC Scheme (2020) (19)
In-DRAM near-data approximate acceleration for GPUs (2018) (19)
NCAP: Network-Driven, Packet Context-Aware Power Management for Client-Server Architecture (2017) (19)
Workload-aware voltage regulator optimization for power efficient multi-core processors (2012) (19)
NetDIMM: Low-Latency Near-Memory Network Interface Architecture (2019) (19)
Time redundant parity for low-cost transient error detection (2011) (18)
Accordion: Toward soft Near-Threshold Voltage Computing (2014) (18)
Near-DRAM Acceleration with Single-ISA Heterogeneous Processing in Standard Memory Modules (2016) (17)
G-Scalar: Cost-Effective Generalized Scalar Execution Architecture for Power-Efficient GPUs (2017) (17)
Don’t Forget the I/O When Allocating Your LLC (2021) (17)
A Linear Algebra Core Design for Efficient Level-3 BLAS (2012) (17)
ScalCore: Designing a core for voltage scalability (2016) (17)
PVT-variations and supply-noise tolerant 45nm dense cache arrays with Diffusion-Notch-Free (DNF) 6T SRAM cells and dynamic multi-Vcc circuits (2008) (16)
SiMul: An Algorithm-Driven Approximate Multiplier Design for Machine Learning (2018) (16)
RCS: Runtime resource and core scaling for power-constrained multi-core processors (2014) (15)
Scratchpad memory optimizations for digital signal processing applications (2011) (15)
Mixed-Signal Charge-Domain Acceleration of Deep Neural Networks through Interleaved Bit-Partitioned Arithmetic (2019) (15)
Runtime temperature-based power estimation for optimizing throughput of thermal-constrained multi-core processors (2010) (14)
Quantitative analysis and optimization techniques for on-chip cache leakage power (2005) (14)
VARIUS-TC: A modular architecture-level model of parametric variation for thin-channel switches (2016) (14)
A 16-GB 640-GB/s HBM2E DRAM With a Data-Bus Window Extension Technique and a Synergetic On-Die ECC Scheme (2021) (13)
Data Direct I/O Characterization for Future I/O System Exploration (2020) (13)
Optimal algorithm for profile-based power gating: A compiler technique for reducing leakage on execution units in microprocessors (2010) (13)
Leveraging Power-Performance Relationship of Energy-Efficient Modern DRAM Devices (2018) (13)
BabelFish: Fusing Address Translations for Containers (2020) (13)
Bit-Parallel Vector Composability for Neural Acceleration (2020) (12)
iPatch: Intelligent fault patching to improve energy efficiency (2015) (12)
Unlocking the Power of Inline Floating-Point Operations on Programmable Switches (2021) (12)
Rebooting the Data Access Hierarchy of Computing Systems (2017) (12)
Exploiting GPU peak-power and performance tradeoffs through reduced effective pipeline latency (2013) (12)
Analyzing and minimizing effects of temperature variation and NBTI on active leakage power of power-gated circuits (2010) (12)
Energy-efficient floating-point arithmetic for software-defined radio architectures (2011) (12)
Total leakage optimization strategies for multi-level caches (2005) (12)
Frequency and yield optimization using power gates in power-constrained designs (2009) (11)
Aquabolt-XL: Samsung HBM2-PIM with in-memory processing for ML accelerators and beyond (2021) (11)
DUANG: Fast and lightweight page migration in asymmetric memory systems (2016) (10)
SRAM dynamic stability estimation using MPFP and its applications (2009) (10)
Load-Triggered Warp Approximation on GPU (2018) (10)
vCache: Architectural support for transparent and isolated virtual LLCs in virtualized environments (2015) (9)
An Efficient GPU Cache Architecture for Applications with Irregular Memory Access Patterns (2019) (9)
Bolt: Faster Reconfiguration in Operating Systems (2015) (9)
CTA-Aware Prefetching and Scheduling for GPU (2018) (9)
Elastic-Cache: GPU Cache Architecture for Efficient Fine- and Coarse-Grained Cache-Line Management (2017) (9)
Workload-Aware Optimal Power Allocation on Single-Chip Heterogeneous Processors (2016) (8)
Improving Throughput of Power-Constrained Many-Core Processors Based on Unreliable Devices (2013) (8)
Ultra-low-power image signal processor for smart camera applications (2015) (8)
Power-performance trade-offs in nanometer-scale multi-level caches considering total leakage (2005) (8)
LL-PCM: Low-Latency Phase Change Memory Architecture (2019) (8)
Decoupled Control and Data Processing for Approximate Near-Threshold Voltage Computing (2015) (8)
Improving platform energy-chip area trade-off in near-threshold computing environment (2013) (7)
Analyzing potential power reduction with adaptive voltage positioning optimized for multicore processors (2009) (7)
Practical Near-Data Processing to Evolve Memory and Storage Devices into Mainstream Heterogeneous Computing Systems (2019) (7)
Exploiting OS-Level Memory Offlining for DRAM Power Management (2019) (6)
Queuing theoretic analysis of power-performance tradeoff in power-efficient computing (2013) (6)
Near-Memory and In-Storage FPGA Acceleration for Emerging Cognitive Computing Workloads (2019) (6)
Workload-adaptive process tuning strategy for power-efficient multi-core processors (2010) (6)
AxMemo: Hardware-Compiler Co-Design for Approximate Code Memoization (2019) (5)
Multiplier supporting accuracy and energy trade-offs for recognition applications (2014) (5)
Optimization of a Cell Counting Algorithm for Mobile Point-of-Care Testing Platforms (2014) (5)
VR-Scale: Runtime dynamic phase scaling of processor voltage regulators for improving power efficiency (2016) (5)
Energy-efficient reconfigurable cache architectures for accelerator-enabled embedded systems (2014) (5)
Mitigating random variation with spare RIBs: Redundant intermediate bitslices (2012) (5)
Virtual Floating-Point Units for Low-Power Embedded Processors (2012) (5)
Exploring new features of high-bandwidth memory for GPUs (2016) (5)
Snatch: Opportunistically reassigning power allocation between processor and memory in 3D stacks (2016) (5)
Fine-Grained Task Migration for Graph Algorithms Using Processing in Memory (2016) (5)
CNFET-Based High Throughput SIMD Architecture (2018) (4)
A load balancing technique for memory channels (2018) (4)
Revamping Storage Class Memory With Hardware Automated Memory-Over-Storage Solution (2021) (4)
Alloy: Parallel-serial memory channel architecture for single-chip heterogeneous processor systems (2015) (4)
Exploring Fault-Tolerant Erasure Codes for Scalable All-Flash Array Clusters (2019) (4)
Understanding power-performance relationship of energy-efficient modern DRAM devices (2017) (4)
QEI: Query Acceleration Can be Generic and Efficient in the Cloud (2021) (4)
CIAO: Cache Interference-Aware Throughput-Oriented Architecture and Scheduling for GPUs (2018) (4)
Simulating PCI-Express Interconnect for Future System Exploration (2018) (4)
Analyzing impact of multiple ABB and AVS domains on throughput of power and thermal-constrained multi-core processors (2010) (4)
Resilient High-Performance Processors with Spare RIBs (2013) (4)
The compatibility analysis of thread migration and DVFS in multi-core processor (2010) (4)
SRAM dynamic stability estimation using MPFP (2007) (4)
NMAP: Power Management Based on Network Packet Processing Mode Transition for Latency-Critical Workloads (2021) (4)
Dynamic bandwidth scaling for embedded DSPs with 3D-stacked DRAM and wide I/Os (2013) (4)
Virtual-Cache: A cache-line borrowing technique for efficient GPU cache architectures (2021) (3)
DiAG: a dataflow-inspired architecture for general-purpose processors (2021) (3)
Doing more with less: training large DNN models on commodity servers for the masses (2021) (3)
Parameter Variation at Near Threshold Voltage : The Power Efficiency versus Resilience Tradeoff (2013) (3)
SpinWise: A Practical Energy-Efficient Synchronization Technique for CMPs (2016) (3)
Maximizing throughput of power/thermal-constrained processors by balancing power consumption of cores (2014) (3)
A low cost approach to calibrate on-chip thermal sensors (2011) (3)
Energy-efficient floating-point arithmetic for digital signal processors (2011) (3)
GreenDIMM: OS-assisted DRAM Power Management for DRAM with a Sub-array Granularity Power-Down State (2021) (3)
Analyzing the performance and energy impact of 3D memory integration on embedded DSPs (2011) (3)
Harmony: Overcoming the hurdles of GPU memory capacity to train massive DNN models on commodity servers (2022) (3)
An FPGA-based RNN-T Inference Accelerator with PIM-HBM (2022) (3)
Leveraging Dynamic Partial Reconfiguration with Scalable ILP Based Task Scheduling (2020) (3)
An 8.5-Gb/s/Pin 12-Gb LPDDR5 SDRAM With a Hybrid-Bank Architecture, Low Power, and Speed-Boosting Techniques (2021) (3)
CNFET-based high throughput register file architecture (2016) (3)
Comparison of single-ISA heterogeneous versus wide dynamic range processors for mobile applications (2015) (3)
Practical Challenges in Supporting Function in Memory (2018) (2)
VIP: Virtual Performance-State for Efficient Power Management of Virtual Machines (2018) (2)
DML: Dynamic Partial Reconfiguration With Scalable Task Scheduling for Multi-Applications on FPGAs (2022) (2)
3D-Xpath: high-density managed DRAM architecture with cost-effective alternative paths for memory transactions (2018) (2)
Impact of Ti Deposition and Subsequent RTA Process on Contact Resistivity Characteristics of W-Bit Line in Sub-Micron Dynamic Random Access Memory (2003) (2)
IMPRoVIng MeMoRy ReLIAbILITy , PoWeR AnD PeRfoRMAnCe UsIng MIxeD-CeLL DesIgns (2013) (2)
An Energy-Efficient Programmable Mixed-Signal Accelerator for Machine Learning Algorithms (2019) (2)
REEL: Reducing effective execution latency of floating point operations (2013) (2)
IDIO: Orchestrating Inbound Network Data on Server Processors (2021) (2)
Understanding system characteristics of online erasure coding on scalable, distributed and large-scale SSD array systems (2017) (2)
Joint optimisation of computational accuracy and algorithm parameters for energy-efficient recognition algorithms (2015) (2)
POWER ANALYZER FOR POCKET COMPUTING (PAPC) (2004) (2)
Erratum: Circuit and microarchitectural techniques for reducing cache leakage power (IEEE Transactions on Very Large Scale Integration (VLSI) Systems (Feb. 2004) 12:2 (167-184)) (2005) (2)
SMART: STT-MRAM architecture for smart activation and sensing (2019) (2)
Design and Implementation of SSD-Assisted Backup and Recovery for Database Systems (2020) (2)
Network Packet Processing Mode-Aware Power Management for Data Center Servers (2020) (2)
Impact of Polymetal Gate Etch Post-Cleaning on Data Retention Time in Sub-micron DRAM Cells (2002) (2)
Impact on Off-state Leakage Current in PMOS Device by Metallic Contamination (2006) (2)
Effect of Ti-rich TiN as a Co-salicide capping layer for 0.15 um embedded flash memory devices and beyond (2006) (2)
Approximate Ultra-Low Voltage Many-Core Processor Design (2018) (2)
A SIMD-MIMD Acceleration with Access-Execute Decoupling for Generative Adversarial Networks (2018) (2)
FReaC Cache: Folded-logic Reconfigurable Computing in the Last Level Cache (2020) (2)
Temporal codes in on-chip interconnects (2017) (2)
OSC: An Online Self-Configuring Big Data Framework for Optimization of QoS (2022) (1)
Maximizing Frequency and Yield of Power-Constrained Designs Using Programmable Power-Gating (2012) (1)
[INVITED] Practical Near-Data Processing to Evolve Memory and Storage Devices into Mainstream Heterogeneous Computing Systems (2019) (1)
Interlayer dielectric (ILD)-related edge channel effect in high density DRAM cell (2002) (1)
Reliability failure induced by the Si epitaxy growth on PMOS high voltage oxide in 0.15/spl mu/m embedded flash memory devices (2004) (1)
Guest Editors' Introduction: Approximate Computing (2016) (1)
Real impact of W/WNx/Poly-Si gate stack in volume production of high density DRAM (2001) (1)
Low-Damage Gate Etching with High Degree of Anisotropy in High-Density DRAM Cell (2002) (1)
Statistical static timing analysis considering leakage variability in power gated designs (2009) (1)
Bit Serializing a Microprocessor for Ultra-low-power (2016) (1)
Quantitative comparison of the power reduction techniques for samsung reconfigurable processor (2014) (1)
Write-after-Read Hazard Prevention in GPGPUsim (2017) (1)
AVS-aware power-gate sizing for maximum performance and power efficiency of power-constrained processors (2011) (1)
Cost-effective, asynchronous inter-sensor distance estimation using trigonometry (2016) (1)
Energy-Efficient Pixel-Arithmetic (2014) (1)
Proceedings of the First International Workshop on Post Moore ' s Era Supercomputing (2016) (1)
A Microarchitectural Model of Process Variation for Near-threshold Computing (2011) (1)
Microarchitectural Power Modeling Techniques for Deep SubMicron (2002) (1)
GPU register file visualization (2015) (1)
Clamping Virtual Supply Voltage of Power-Gated Circuits for Active Leakage Reduction and Gate-Oxide Reliability (2013) (1)
Defensive ML: Defending Architectural Side-channels with Adversarial Obfuscation (2023) (0)
FastDrain: Removing Page Victimization Overheads in NVMe Storage Stack (2020) (0)
Impact of untreated thicker CVD TiN film at a Via glue layer on Rc Performance in 0.15um CMOS Technology (2006) (0)
Janus: supporting heterogeneous power management in virtualized environments (2017) (0)
Spare RIBs: Redundant Intermediate Bitslices (2011) (0)
Improving performance, power efficiency, yield, and reliability using programmable power-gating techniques (2012) (0)
HAMS: Hardware Automated Memory-over-Storage for Large-scale Memory Expansion (2022) (0)
Errata to "Exploring Fault-Tolerant Erasure Codes for Scalable All-Flash Array Clusters" (2020) (0)
Online and Operand-Aware Detection of Failures Utilizing False Alarm Vectors (2015) (0)
A μ − architectural Model of Process Variation for Near-Threshold Computing (2011) (0)
Effect of Poly Metal Gate Etch Post-Cleaning on the Tail Distribution of DRAM Data Retention Time (2001) (0)
Runtime memory optimization and GPU / manycore architectures (2017) (0)
Ghost routers: energy-efficient asymmetric multicore processors with symmetric NoCs (2019) (0)
Suppression of Short Channel Hump of nMOSFET Using NF3-Added ILD HDP Process (2002) (0)
CREATING A PCI EXPRESS INTERCONNECT IN THE GEM5 SIMULATOR BY KRISHNA PARASURAM SRINIVASAN THESIS Submitted in partial fulfillment of the requirements for the degree of Master of Science in Electrical and Computer Engineering (2018) (0)
Demystifying CXL Memory with Genuine CXL-Ready Systems and Devices (2023) (0)
Semi-Coherent DMA: An Alternative I/O Coherency Management for Embedded Systems (2018) (0)
Effect of checker board failure on yield improvement in 0.15 /spl mu/m embedded flash memory (2005) (0)
Analysis of Low Leakage and High Performance 4 bit CLA Full Adder (2020) (0)
ORCA: A Network and Architecture Co-design for Offloading us-scale Datacenter Applications (2022) (0)
Investigation on Metal Pillar Defect in sub-micron CMOS Technology (2006) (0)
Low-cost scratchpad memory organizations using heterogeneous cell sizes for low-voltage operations (2014) (0)
A new low temperature APM cleaning process to improve ONO integrity in 0.18μm stacked-gate EEPROM memory (2005) (0)
Optimization of n-junction through ion beam shadowing and buffering effect by tilt implantation with rotation for improving the retention time (2000) (0)
Novel High-Performance Analog Devices for Advanced Low-Power High-k Metal Gate Complementary Metal–Oxide–Semiconductor Technology (2011) (0)
IOCA: High-Speed I/O-Aware LLC Management for Network-Centric Multi-Tenant Platform (2020) (0)
Improvement of Disturbance/Pause Retention Time by Reducing Edge Channel Effect of Cell in Gigabit Density DRAMs and beyond (2002) (0)
Impact of Ti Deposition Condition and Subsequent RTA on Contact Resistance of W-Bit Line in sub-micron technology DRAM (2002) (0)
DRAM Reliability Degradation By Dynamic Operation Stress During Burn-In (2003) (0)
A Quantitative Analysis and Guideline of Data Streaming Accelerator in Intel 4th Gen Xeon Scalable Processors (2023) (0)
A2M: Approximate Algebraic Memory Using Polynomials Rings (2019) (0)
Impact of Co-salicide capping layer on GIDL in High Voltage devices for Embedded Flash memory (2004) (0)
Control gate-bit line leakage induced cobalt silicide migration in 0.15/spl mu/m embedded flash memory devices (2005) (0)
Improvement of the tail component in retention time distribution using buffered n-implantation with tilt and rotation (BNITR) for 0.2 um DRAM cell and beyond (2000) (0)
Effect of magnetic field on plasma damage during VIA etching in sub-micron CMOS technology (2004) (0)
Controlling the voltage supply of a memory cell due to error detection (2007) (0)
Impact of Gate Etch l ) amage and Profile in High Density DRAM CeIl A-2-4 (2008) (0)
Successful fault isolation of bit line leakage and leakage suppression by ILD optimization in embedded flash memory (2005) (0)
A-7 . 2 Improvement of DisturbancelPause Retentlsl Time by Reducing Edge Channel Effect sf CeIl in Gigabit Density DRAMs and beyond (2008) (0)
Impact of Burn-In Stress on Reliability of High Density DRAMs (2002) (0)
4 Runtime memory optimization and GPU / manycore architectures (2017) (0)
Impact of Gate Etch Damage and Profile in High Density DRAM Cell (2001) (0)
Optimizing throughput and power consumption of graphics processing units (gpus) (2013) (0)

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Other Resources About Nam Sung Kim

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What Schools Are Affiliated With Nam Sung Kim?

Nam Sung Kim is affiliated with the following schools: