Robert H. Dennard | Academic Influence

Robert H. Dennard's AcademicInfluence.com Rankings

Robert H. Dennard

Engineering

#61

World Rank

#129

Historical Rank

#31

USA Rank

Electrical Engineering

#38

World Rank

#46

Historical Rank

#24

USA Rank

Applied Physics

#2950

World Rank

#3011

Historical Rank

#289

USA Rank

engineering Degrees

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Engineering

Why Is Robert H. Dennard Influential?

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According to Wikipedia, Robert Heath Dennard is an American electrical engineer and inventor. Biography Dennard was born in Terrell, Texas, U.S. He received his B.S. and M.S. degrees in Electrical Engineering from Southern Methodist University, Dallas, in 1954 and 1956, respectively. He earned a Ph.D. from Carnegie Institute of Technology in Pittsburgh, Pennsylvania, in 1958. His professional career was spent as a researcher for International Business Machines.

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Robert H. Dennard's Published Works

Number of citations in a given year to any of this author's works

Total number of citations to an author for the works they published in a given year. This highlights publication of the most important work(s) by the author

Published Works

Design Of Ion-implanted MOSFET's with Very Small Physical Dimensions (1974) (2028)
Device scaling limits of Si MOSFETs and their application dependencies (2001) (1416)
Stable SRAM cell design for the 32 nm node and beyond (2005) (585)
An 8T-SRAM for Variability Tolerance and Low-Voltage Operation in High-Performance Caches (2008) (429)
Generalized scaling theory and its application to a ¼ micrometer MOSFET design (1984) (427)
Silicon CMOS devices beyond scaling (2006) (401)
CMOS scaling for high performance and low power-the next ten years (1995) (388)
When are transmission-line effects important for on-chip interconnections? (1997) (356)
1 µm MOSFET VLSI technology: Part IV—Hot-electron design constraints (1979) (227)
Challenges and future directions for the scaling of dynamic random-access memory (DRAM) (2002) (221)
Practical Strategies for Power-Efficient Computing Technologies (2010) (189)
Iddq test: sensitivity analysis of scaling (1996) (166)
A fully-integrated switched-capacitor 2∶1 voltage converter with regulation capability and 90% efficiency at 2.3A/mm2 (2010) (162)
Modeling and characterization of long on-chip interconnections for high-performance microprocessors (1995) (159)
Submicrometer-channel CMOS for low-temperature operation (1987) (125)
Design and experimental technology for 0.1-µm gate-length low-temperature operation FET's (1987) (117)
Design of micron MOS switching devices (2007) (109)
Alpha-Particle-Induced Soft Error Rate in VLSI Circuits (1982) (103)
A 30 Year Retrospective on Dennard's MOSFET Scaling Paper (2007) (94)
A perspective on today’s scaling challenges and possible future directions (2007) (82)
A 3-Transistor DRAM Cell with Gated Diode for Enhanced Speed and Retention Time (2006) (78)
A Room Temperature 0.1 /spl mu/m CMOS on SOI (1993) (77)
Design of ion-implanted MOSFET's with very small physical dimensions (1999) (77)
1 µm MOSFET VLSI technology: Part II—Device designs and characteristics for high-performance logic applications (1979) (70)
High performance extremely thin SOI (ETSOI) hybrid CMOS with Si channel NFET and strained SiGe channel PFET (2012) (68)
When are transmission-line effects important for on-chip interconnections (1997) (58)
Iddq testing for high performance CMOS-the next ten years (1996) (55)
CMOS with active well bias for low-power and RF/analog applications (2000) (51)
Fabrication of a miniature 8K‐bit memory chip using electron‐beam exposure (1975) (49)
Channel profile optimization and device design for low-power high-performance dynamic-threshold MOSFET (1996) (49)
A self-aligned 1-µm-channel CMOS technology with retrograde n-well and thin epitaxy (1985) (46)
1 pm MOSFET VLSI Technology: Part lV— Hot-Electron Design Constraints (1979) (45)
A novel dynamic memory cell with internal voltage gain (2005) (41)
CMOS scaling in the 0.1-µm, 1.X-volt regime for high-performance applications (1995) (38)
Experimental technology and performance of 0.1-mm-gate-length FETs operated at liquid nitrogen temperature (1990) (38)
1 /spl mu/m MOSFET VLSI technology. IV. Hot-electron design constraints (1979) (38)
1 /spl mu/m MOSFET VLSI technology. II. Device designs and characteristics for high-performance logic applications (1979) (37)
Scalability and biasing strategy for CMOS with active well bias (2001) (32)
Gated-diode amplifiers (2005) (31)
SOI for a 1-volt CMOS technology and application to a 512 Kb SRAM with 3.5 ns access time (1993) (30)
Evolution of the MOSFET dynamic RAM—A personal view (1984) (29)
Soft error rate scaling for emerging SOI technology options (2002) (29)
Transient pass-transistor leakage current in SOI MOSFET's (1997) (29)
Experimental technology and characterization of self-aligned 0.1µm-gate-length low-temperature operation NMOS devices (1987) (29)
Theoretical determination of the temporal and spatial structure of /spl alpha/-particle induced electron-hole pair generation in silicon (2000) (28)
History dependence of non-fully depleted (NFD) digital SOI circuits (1996) (24)
Characterization and modeling of a latchup-free 1-µm CMOS technology (1984) (23)
IIA-1 generalized scaling theory and its application to a 1/4 micron mosfet design (1982) (22)
Design guidelines for short, medium, and long on-chip interconnections (1996) (21)
Threshold voltage characteristics of depletion-mode MOSFET's (1981) (20)
Design and characterization of a CMOS off-chip driver/receiver with reduced power-supply disturbance (1992) (19)
High-performance Si1−xGex channel on insulator trigate PFETs featuring an implant-free process and aggressively-scaled fin and gate dimensions (2013) (18)
Inverter performance of deep-submicrometer MOSFETs (1988) (17)
A Self-Aliglned 1-/spl mu/m-Channel CMOS Technology with Retrograde n-Well and Thin Epitaxy (1985) (16)
A buried N-grid for protection against radiation induced charge collection in electronic circuits (1981) (15)
A fully scaled submicrometer NMOS technology using direct-write E-beam lithography (1985) (15)
Technologies to further reduce soft error susceptibility in SOI (2009) (15)
Supply voltage strategies for minimizing the power of CMOS processors (2002) (15)
Power-supply considerations for future scaled CMOS systems (1989) (14)
A 4 Mb Low-temperature DRAM (1991) (14)
Past Progress and Future Challenges in LSI Technology: From DRAM and Scaling to Ultra-Low-Power CMOS (2015) (14)
Ion implanted MOSFETs with very short channel lengths (1973) (13)
Technology challenges for ultrasmall silicon MOSFET's (1981) (13)
Iddq Testing for High Performance CMOS - The Next Ten Years (1996) (13)
2T1D memory cell with voltage gain (2004) (12)
A Hardened Field Insulator (1981) (11)
0.5 Micron Gate CMOS Technology Using E-Beam/Optical Mix Lithography (1986) (11)
Floating-body concerns for SOI dynamic random access memory (DRAM) (1996) (10)
Creativity in the 2000s and Beyond (2000) (10)
IGFET circuit performance-n-channel versus p-channel (1969) (9)
Physical limits to VLSI technology using silicon MOSFET's (1983) (9)
Hot-electron design constraints for one-micron IGFET's (1978) (9)
1-GHz fully pipelined 3.7-ns address access time 8 k/spl times/1024 embedded synchronous DRAM macro (2000) (9)
Technical literature [Reprint of "Field-Effect Transistor Memory" (US Patent No. 3,387,286)] (2008) (8)
SOI for Low-Voltage and High-Speed CMOS (1994) (8)
An experimental high-density memory array fabricated with electron beam (1972) (8)
MOSFET designs and characteristics for high performance logic at micron dimensions (1978) (8)
A Vestigial-Sideband, Phase-Reversal Data Transmission System (1964) (7)
CMOS technology for low voltage/low power applications (1994) (7)
Design and characteristics of n-channel insulated-gate field-effect transistors (2000) (7)
MOSFET miniaturization — From one micron to the limits (1985) (6)
FDSOI CMOS with dielectrically-isolated back gates and 30nm LG high-γ/metal gate (2010) (6)
Accurate measurement of pass-transistor leakage current in SOI MOSFET's (1996) (6)
Practical Strategies for Power-Efficient Computing (2010) (5)
Design and fabrication of p-channel FET for 1-µm CMOS technology (1982) (5)
Scaling Limits of Silicon VLSI Technology (1986) (5)
WP 24.3 1GHz Fully Pipelined 3.7ns Address Access Time 8kx1024 Embedded DRAM Macro (2000) (5)
Behavior of the ferroresonant series circuit containing a square-loop reactor (1959) (5)
Revisiting "Evolution of the MOSFET Dynamic RAM – A Personal View" (2008) (5)
0.5µm-channel CMOS technology optimized for liquid-nitrogen-temperature operation (1986) (5)
A 34 /spl mu/m/SUP 2/ DRAM cell fabricated with a 1 /spl mu/m single-level polycide FET technology (1981) (5)
Future CMOS Scaling-Approaching the Limits? (1996) (4)
Advanced FDSOI Device Design: The U-Channel Device for 7 nm Node and Beyond (2018) (4)
FDSOI CMOS with dual backgate control for performance and power modulation (2009) (3)
1 GHz fully pipelined 3.7 ns address access time 8 k/spl times/1024 embedded DRAM macro (2000) (3)
Modeling and Control of Alpha-Particle Effects in Scaled-Down VLSI Circuits (1981) (3)
Ion implanted MOSFET's with very short channel lengths (2007) (3)
A Fully Scaled Half-Micrometer NMOS Technology Using Direct-Write E-Beam Lithography (1984) (2)
How we made DRAM (2018) (2)
A High Performance Liquid-Nitrogen CMOS SRAM Technology (1988) (2)
A self-aligned 1-µm CMOS technology for VLSI (1983) (2)
Carrier Confinement in UTSOI Devices : Impact of Metal Gate Work Function (2005) (2)
A CMOS Off-Chip Driver/Receiver with Reduced Signal Swing and Reduced Power-Supply Disturbance (1991) (1)
Simulation Study on Channel Length Scaling of High Performance Partially Depleted Metal Gate and Poly Gate SOI MOSFETs (2006) (1)
Miniaturization Limits for Mos Technology (1982) (1)
1 – A Perspective on Today’s Scaling Challenges and Possible Future Directions1 (2012) (1)
High-performance Si1−xGex channel on insulator trigate PFETs featuring an implant-free process and aggressively-scaled fin and gate dimensions (2013) (1)
35nm SOI-CMOS for Sub-Ambient Temperature Operation (2007) (0)
A 40-year Perspective on Scaling (2012) (0)
A process for preparing oxide-isolated field effect transistors (1975) (0)
Components-threshold control of a front-gate silicon-on-insulator-mosfet using a self-aligned back-gate (2004) (0)
Circuit arrangement for the indication of the displacement of electric charge (1975) (0)
Patents Recently Issued to IBM Inventors (1967) (0)
A 34µm2DRAM cell fabricated with a 1µm single-level polycide FET technology (1981) (0)
Silicon and formation thereof (1992) (0)
Integrated Circuits: 50 Years of Their Evolution and Future Prospects ―Towards Higher-Density Memories and Ultra-Low Power LSIs― (2013) (0)
How we made DRAM (2018) (0)
Simulation Studyon Channel LengthScalingof High Performance Partially Depleted MetalGate (2006) (0)
The progress in miniaturization of MOSFET devices and integrated circuits has continued steadily. Even while development work using IJLm dimensions is building up, exploratory efforts in submicron devices has begun. Government funding has served to stimulate this (1982) (0)
A Perspective on Today’s Scaling Challenges and Possible Future Directions * *This chapter appeared in Solid State Electronics, 51(4) (2007) 518–525. Copyright © 2007 Elsevier Ltd. (2018) (0)
MA-4 the evolution of MOS technology toward VLSI (1979) (0)
Session 9 nonvolatile memories [breaker page] (1982) (0)
A Quarterback's Passion and Desire to Win [People] (2021) (0)
Challenges future directions the scaling of dynamic random-access (DRAM) (2002) (0)
The Evolution of Microelectronics : Some History and a Current Perspective (1992) (0)
A method of forming a semiconductor wafer for integrated circuit structure units (2010) (0)
0.5 μm CMOS Device Design and Characterization (1987) (0)
Advanced Silicon MOS Devices and Related Problems (1982) (0)
A process for the preparation of defect-free silicon on an insulating substrate (1992) (0)
Silicon-on-insulator wafer with the hybrid double-box back gate and channels with improved mobility (2010) (0)
Advanced FDSOI design: The U-channel device for 7nm node and beyond (2017) (0)

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What Schools Are Affiliated With Robert H. Dennard?

Robert H. Dennard is affiliated with the following schools:

Carnegie Mellon University

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