Mateo Valero
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Spanish computer architect
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Why Is Mateo Valero Influential?
(Suggest an Edit or Addition)According to Wikipedia, Mateo Valero Cortés is a Spanish computer architect. His research encompasses different concepts within the field of computer architecture, a discipline in which he has published more than 700 papers in journals, conference proceedings and books. Valero has received numerous awards, including the Eckert–Mauchly Award in 2007, for "extraordinary leadership in building a world class computer architecture research center, for seminal contributions in the areas of vector computing and multithreading, and for pioneering basic new approaches to instruction-level parallelism." He is the director of the Barcelona Supercomputing Center, which hosts the MareNostrum supercomputer.
Mateo Valero's Published Works
Number of citations in a given year to any of this author's works
Total number of citations to an author for the works they published in a given year. This highlights publication of the most important work(s) by the author
Published Works
- The International Exascale Software Project roadmap (2011) (735)
- Multiple-banked register file architectures (2000) (437)
- Hardware support for WCET analysis of hard real-time multicore systems (2009) (290)
- Parallel Computer Architecture (2000) (217)
- A data cache with multiple caching strategies tuned to different types of locality (1995) (194)
- Enabling preemptive multiprogramming on GPUs (2014) (186)
- A data cache with multiple caching strategies tuned to different types of locality (1995) (172)
- Dynamically Controlled Resource Allocation in SMT Processors (2004) (168)
- Supercomputing with commodity CPUs: Are mobile SoCs ready for HPC? (2013) (167)
- An Analyzable Memory Controller for Hard Real-Time CMPs (2009) (167)
- Performance, power efficiency and scalability of asymmetric cluster chip multiprocessors (2006) (165)
- Improving Cache Management Policies Using Dynamic Reuse Distances (2012) (158)
- Alya: Multiphysics engineering simulation toward exascale (2016) (151)
- Out-of-order commit processors (2004) (148)
- Eliminating cache conflict misses through XOR-based placement functions (1997) (147)
- Fuzzy memoization for floating-point multimedia applications (2005) (146)
- Discrete Optimization Problem in Local Networks and Data Alignment (1987) (141)
- Swing module scheduling: a lifetime-sensitive approach (1996) (141)
- Bandwidth of Crossbar and Multiple-Bus Connections for Multiprocessors (1982) (127)
- Virtual-physical registers (1998) (126)
- Task Superscalar: An Out-of-Order Task Pipeline (2010) (115)
- EazyHTM: EAger-LaZY hardware Transactional Memory (2009) (115)
- Multicore Resource Management (2008) (111)
- Partitioning: An Essential Step in Mapping Algorithms Into Systolic Array Processors (1987) (110)
- Vector architectures: past, present and future (1998) (104)
- Overlapping communication and computation by using a hybrid MPI/SMPSs approach (2010) (99)
- Atomic quake: using transactional memory in an interactive multiplayer game server (2009) (93)
- Two-level hierarchical register file organization for VLIW processors (2000) (92)
- Delaying physical register allocation through virtual-physical registers (1999) (91)
- Predictable performance in SMT processors: synergy between the OS and SMTs (2006) (88)
- Transactional Memory: An Overview (2007) (88)
- Toward kilo-instruction processors (2004) (87)
- The International Exascale Software Project: a Call To Cooperative Action By the Global High-Performance Community (2009) (83)
- Understanding the future of energy-performance trade-off via DVFS in HPC environments (2012) (82)
- Trace-driven simulation of multithreaded applications (2011) (81)
- Code layout optimizations for transaction processing workloads (2001) (77)
- Out-of-order vector architectures (1997) (76)
- Optimizing job performance under a given power constraint in HPC centers (2010) (70)
- Hypernode reduction modulo scheduling (1995) (69)
- The HiPEAC Vision (2010) (68)
- Moving from petaflops to petadata (2013) (67)
- Decoupled vector architectures (1996) (67)
- A performance characterization of high definition digital video decoding using H.264/AVC (2005) (66)
- Assessing Accelerator-Based HPC Reverse Time Migration (2011) (65)
- On-the-Fly Adaptive Routing in High-Radix Hierarchical Networks (2012) (65)
- Kilo-instruction processors: overcoming the memory wall (2005) (65)
- FlexDCP: a QoS framework for CMP architectures (2009) (64)
- A dynamic scheduler for balancing HPC applications (2008) (64)
- The limits of software transactional memory (STM): dissecting Haskell STM applications on a many-core environment (2008) (64)
- A Flexible Heterogeneous Multi-Core Architecture (2007) (63)
- TERAFLUX: Harnessing dataflow in next generation teradevices (2014) (63)
- QuakeTM: parallelizing a complex sequential application using transactional memory (2009) (63)
- Increasing the Number of Strides for Conflict-free Vector Access (1992) (62)
- Exploiting a new level of DLP in multimedia applications (1999) (61)
- Parallel job scheduling for power constrained HPC systems (2012) (61)
- Lifetime-Sensitive Modulo Scheduling in a Production Environment (2001) (61)
- Command vector memory systems: high performance at low cost (1998) (60)
- Proceedings of the 2nd conference on Computing frontiers (2005) (60)
- Criticality-Aware Dynamic Task Scheduling for Heterogeneous Architectures (2015) (59)
- The Mont-Blanc Prototype: An Alternative Approach for HPC Systems (2016) (59)
- Modulo scheduling with integrated register spilling for clustered VLIW architectures (2001) (58)
- A Quantitative Analysis of OS Noise (2011) (55)
- On the simulation of large-scale architectures using multiple application abstraction levels (2012) (55)
- Large virtual robs by processor checkpointing (2002) (55)
- A content aware integer register file organization (2004) (55)
- QoS for high-performance SMT processors in embedded systems (2004) (54)
- Adapting cache partitioning algorithms to pseudo-LRU replacement policies (2010) (53)
- CODOMs: Protecting software with Code-centric memory Domains (2014) (53)
- Predictable performance in SMT processors (2004) (52)
- Parallel computing and transputer applications (1992) (50)
- Adding a vector unit to a superscalar processor (1999) (50)
- Scalability of Macroblock-level Parallelism for H.264 Decoding (2009) (49)
- Hardware schemes for early register release (2002) (49)
- Efficient Routing Mechanisms for Dragonfly Networks (2013) (48)
- Software-Controlled Priority Characterization of POWER5 Processor (2008) (46)
- MLP-Aware Dynamic Cache Partitioning (2007) (46)
- Design and implementation of high-performance memory systems for future packet buffers (2003) (46)
- Speculative dynamic vectorization (2002) (45)
- Oblivious routing schemes in extended generalized Fat Tree networks (2009) (45)
- Improving Memory Latency Aware Fetch Policies for SMT Processors (2003) (45)
- Fetching instruction streams (2002) (45)
- Conflict-Free Access for Streams in Multimodule Memories (1995) (44)
- Optimal task assignment in multithreaded processors: a statistical approach (2012) (43)
- IA^3: An Interference Aware Allocation Algorithm for Multicore Hard Real-Time Systems (2011) (43)
- Heuristics for register-constrained software pipelining (1996) (42)
- Task Scheduling Techniques for Asymmetric Multi-Core Systems (2017) (42)
- PARSECSs: Evaluating the Impact of Task Parallelism in the PARSEC Benchmark Suite (2016) (41)
- Exploiting instruction- and data-level parallelism (1997) (41)
- Software Trace Cache (2014) (41)
- Utilization driven power-aware parallel job scheduling (2010) (41)
- Implementing Kilo-Instruction Multiprocessors (2005) (40)
- A decoupled KILO-instruction processor (2006) (40)
- Discovering and understanding performance bottlenecks in transactional applications (2010) (39)
- HD-VideoBench. A Benchmark for Evaluating High Definition Digital Video Applications (2007) (39)
- Runtime-Aware Architectures: A First Approach (2014) (39)
- The TERAFLUX Project: Exploiting the DataFlow Paradigm in Next Generation Teradevices (2013) (38)
- Advanced Pattern based Memory Controller for FPGA based HPC applications (2014) (38)
- FAME: FAirly MEasuring Multithreaded Architectures (2007) (37)
- Prophet/critic hybrid branch prediction (2004) (37)
- Reduction of Connections for Multibus Organization (1983) (36)
- Taking the heat off transactions: Dynamic selection of pessimistic concurrency control (2009) (36)
- New Benchmarking Methodology and Programming Model for Big Data Processing (2015) (35)
- Static locality analysis for cache management (1997) (35)
- Multithreaded vector architectures (1997) (34)
- Dcache Warn: an I-fetch policy to increase SMT efficiency (2004) (34)
- Dynamic Tolerance Region Computing for Multimedia (2012) (33)
- Non-consistent dual register files to reduce register pressure (1995) (33)
- Trace cache redundancy: red and blue traces (2000) (32)
- Exploiting asynchrony from exact forward recovery for DUE in iterative solvers (2015) (32)
- WormBench: a configurable workload for evaluating transactional memory systems (2008) (32)
- Performance Impact of Unaligned Memory Operations in SIMD Extensions for Video Codec Applications (2007) (32)
- Software management of selective and dual data caches (1997) (32)
- unreadTVar: Extending Haskell Software Transactional Memory for Performance (2007) (31)
- Tackling IoT Ultra Large Scale Systems: Fog Computing in Support of Hierarchical Emergent Behaviors (2018) (31)
- RMS-TM: a comprehensive benchmark suite for transactional memory systems (2011) (31)
- Characterizing the resource-sharing levels in the UltraSPARC T2 processor (2009) (30)
- MOM: a Matrix SIMD Instruction Set Architecture for Multimedia Applications (1999) (30)
- M-users B-servers arbiter for multiple-busses multiprocessors (1982) (30)
- Detecting and Using Affinity in an Automatic Data Distribution Tool (1994) (29)
- Vector Extensions for Decision Support DBMS Acceleration (2012) (29)
- Debugging programs that use atomic blocks and transactional memory (2010) (29)
- Explaining Dynamic Cache Partitioning Speed Ups (2007) (29)
- Power-aware load balancing of large scale MPI applications (2009) (29)
- Emergent Behaviors in the Internet of Things: The Ultimate Ultra-Large-Scale System (2016) (29)
- Coherence protocol for transparent management of scratchpad memories in shared memory manycore architectures (2015) (29)
- MUSA: A Multi-level Simulation Approach for Next-Generation HPC Machines (2016) (28)
- Runahead Threads to improve SMT performance (2008) (27)
- Dynamically Filtering Thread-Local Variables in Lazy-Lazy Hardware Transactional Memory (2009) (27)
- Spark deployment and performance evaluation on the MareNostrum supercomputer (2015) (27)
- Power and thermal characterization of POWER6 system (2010) (27)
- Software and Hardware Techniques to Optimize Register File Utilization in VLIW Architectures (2004) (27)
- Architectural support for real-time task scheduling in SMT processors (2005) (26)
- FIMSIM: A fault injection infrastructure for microarchitectural simulators (2011) (26)
- Thread Assignment of Multithreaded Network Applications in Multicore/Multithreaded Processors (2013) (26)
- Late allocation and early release of physical registers (2004) (26)
- Exploring pattern-aware routing in generalized fat tree networks (2009) (26)
- Virtual registers (1997) (25)
- Transactional Memory and OpenMP (2007) (25)
- Energy-Aware Accounting and Billing in Large-Scale Computing Facilities (2011) (25)
- A DRAM/SRAM memory scheme for fast packet buffers (2006) (25)
- Dissecting Transactional Executions in Haskell (2007) (24)
- Simulating Whole Supercomputer Applications (2011) (24)
- A Highly Scalable Parallel Implementation of H.264 (2011) (24)
- Linear programming based parallel job scheduling for power constrained systems (2011) (24)
- Scaling Irregular Applications through Data Aggregation and Software Multithreading (2014) (24)
- Designing OS for HPC Applications: Scheduling (2010) (24)
- Balancing HPC applications through smart allocation of resources in MT processors (2008) (23)
- Hierarchical clustered register file organization for VLIW processors (2003) (23)
- The effect of code reordering on branch prediction (2000) (22)
- A case for resource-conscious out-of-order processors (2004) (22)
- Interconnection Networks in Petascale Computer Systems (2016) (22)
- Runtime Aware Architectures (2016) (22)
- Improved spill code generation for software pipelined loops (2000) (22)
- Software trace cache (1999) (21)
- Conflict-free access of vectors with power-of-two strides (1992) (21)
- Contention-Based Nonminimal Adaptive Routing in High-Radix Networks (2015) (21)
- High Performance Computing — HiPC 2000 (2001) (20)
- Effective communication and computation overlap with hybrid MPI/SMPSs (2010) (20)
- Direct Inter-Process Communication (dIPC): Repurposing the CODOMs Architecture to Accelerate IPC (2017) (20)
- Architectural Support for Fair Reader-Writer Locking (2010) (20)
- Modulo Scheduling with Reduced Register Pressure (1998) (20)
- RVC: a mechanism for time-analyzable real-time processors with faulty caches (2011) (19)
- STM2: A Parallel STM for High Performance Simultaneous Multithreading Systems (2011) (19)
- Clock gate on abort: Towards energy-efficient hardware Transactional Memory (2009) (19)
- Kilo-instruction Processors (2003) (19)
- Increasing multicore system efficiency through intelligent bandwidth shifting (2015) (19)
- Performance Analysis of Sequence Alignment Applications (2006) (19)
- OFAR-CM: Efficient Dragonfly Networks with Simple Congestion Management (2013) (18)
- Power and performance aware reconfigurable cache for CMPs (2010) (18)
- Multithreaded software transactional memory and OpenMP (2007) (18)
- Reducing Data Movement on Large Shared Memory Systems by Exploiting Computation Dependencies (2018) (18)
- Fog Function Virtualization: A flexible solution for IoT applications (2017) (18)
- Register constrained modulo scheduling (2004) (18)
- Thread Assignment in Multicore/Multithreaded Processors: A Statistical Approach (2016) (18)
- Using Sacks to Organize Registers in VLIW Machines (1994) (18)
- Programmability and portability for exascale: Top down programming methodology and tools with StarSs (2013) (18)
- Hardware support for accurate per-task energy metering in multicore systems (2013) (18)
- ITCA: Inter-task Conflict-Aware CPU Accounting for CMPs (2009) (17)
- Stencil codes on a vector length agnostic architecture (2018) (17)
- MultiLayer processing - an execution model for parallel stateful packet processing (2008) (17)
- Simultaneous multithreaded vector architecture: merging ILP and DLP for high performance (1997) (17)
- A first glance at Kilo-instruction based multiprocessors (2004) (17)
- On the potential of tolerant region reuse for multimedia applications (2001) (17)
- CPU Accounting for Multicore Processors (2012) (17)
- Available task-level parallelism on the Cell BE (2009) (17)
- Widening resources: a cost-effective technique for aggressive ILP architectures (1998) (17)
- Cost-effective compiler directed memory prefetching and bypassing (2002) (16)
- Evaluating the Impact of OpenMP 4.0 Extensions on Relevant Parallel Workloads (2015) (16)
- Vector multiprocessors with arbitrated memory access (1995) (16)
- Optimizing computation-communication overlap in asynchronous task-based programs (2019) (16)
- Runtime-Guided Mitigation of Manufacturing Variability in Power-Constrained Multi-Socket NUMA Nodes (2016) (16)
- Using a Reconfigurable L1 Data Cache for Efficient Version Management in Hardware Transactional Memory (2011) (16)
- The international race towards Exascale in Europe (2019) (16)
- Picos: A hardware runtime architecture support for OmpSs (2015) (16)
- Enlarging Instruction Streams (2007) (15)
- Quantifying the Potential Task-Based Dataflow Parallelism in MPI Applications (2011) (15)
- Long DNA Sequence Comparison on Multicore Architectures (2010) (15)
- A low-complexity, high-performance fetch unit for simultaneous multithreading processors (2004) (15)
- Runtime-Guided Management of Stacked DRAM Memories in Task Parallel Programs (2018) (15)
- Performance analysis of a hardware accelerator of dependence management for task-based dataflow programming models (2016) (15)
- VSR sort: A novel vectorised sorting algorithm & architecture extensions for future microprocessors (2015) (15)
- MIRS: Modulo Scheduling with Integrated Register Spilling (2001) (15)
- Direct Instruction Wakeup for Out-of-Order Processors (2004) (15)
- Quantitative analysis of vector code (1995) (15)
- A Simulator for SMT Architectures: Evaluating Instruction Cache Topologies (2000) (15)
- CPU Accounting in CMP Processors (2009) (15)
- Optimising long-latency-load-aware fetch policies for SMT processors (2004) (15)
- Stand-Alone Memory Controller for Graphics System (2014) (14)
- Enhancing and Exploiting the Locality (1999) (14)
- A Two-Level Load/Store Queue Based on Execution Locality (2008) (14)
- Task superscalar: using processors as functional units (2010) (14)
- An ISA Comparison Between Superscalar and Vector Processors (1998) (14)
- Using Arm’s scalable vector extension on stencil codes (2019) (14)
- Runtime-Guided Management of Scratchpad Memories in Multicore Architectures (2015) (14)
- Register Requirements Of Pipelined Loops And Their Effect On Performance (1994) (14)
- Evaluating the Impact of TLB Misses on Future HPC Systems (2012) (14)
- Align and Distribute-based Linear Loop Transformations (1993) (13)
- Computing size-independent matrix problems on systolic array processors (1986) (13)
- Quantitative Evaluation of Register Pressure on Software Pipelined Loops (1998) (13)
- A vector-/spl mu/SIMD-VLIW architecture for multimedia applications (2005) (13)
- SymptomTM: Symptom-Based Error Detection and Recovery Using Hardware Transactional Memory (2011) (13)
- DLP+TLP processors for the next generation of media workloads (2001) (13)
- Thread Lock Section-Aware Scheduling on Asymmetric Single-ISA Multi-Core (2015) (13)
- A Hardware Runtime for Task-Based Programming Models (2019) (13)
- Three-dimensional memory vectorization for high bandwidth media memory systems (2002) (12)
- Online Prediction of Applications Cache Utility (2007) (12)
- General Purpose Task-Dependence Management Hardware for Task-Based Dataflow Programming Models (2017) (12)
- A Comprehensive Analysis of Indirect Branch Prediction (2002) (12)
- Parallel processing in biological sequence comparison using general purpose processors (2005) (12)
- Dynamic Register Renaming Through Virtual-Physical Registers (2000) (12)
- Efficient Sorting on the Tilera Manycore Architecture (2012) (12)
- Performance evaluation of macroblock-level parallelization of H.264 decoding on a cc-NUMA multiprocessor architecture (2009) (12)
- A performance evaluation of the multiple bus network for multiprocessor systems (1983) (12)
- Improving Accuracy and Speeding Up Document Image Classification Through Parallel Systems (2020) (12)
- Power efficient job scheduling by predicting the impact of processor manufacturing variability (2019) (12)
- Architectural impact of stateful networking applications (2005) (12)
- Measuring Operating System Overhead on CMT Processors (2008) (11)
- Thread to Core Assignment in SMT On-Chip Multiprocessors (2009) (11)
- APPLE: Adaptive Performance-Predictable Low-Energy caches for reliable hybrid voltage operation (2013) (11)
- RVC-based time-predictable faulty caches for safety-critical systems (2011) (11)
- Optimization of instruction fetch for decision support workloads (1999) (11)
- ATM: Approximate Task Memoization in the Runtime System (2017) (11)
- Increasing effective IPC by exploiting distant parallelism (1999) (11)
- Evaluation of vectorization potential of Graph500 on Intel's Xeon Phi (2014) (11)
- CATA: Criticality Aware Task Acceleration for Multicore Processors (2016) (11)
- A Simulation Framework to Automatically Analyze the Communication-Computation Overlap in Scientific Applications (2010) (11)
- Solving Matrix Problems with No Size Restriction on a Systolic Array Processor (1986) (11)
- An asymmetric clustered processor based on value content (2005) (11)
- Circuit design of a dual-versioning L1 data cache for optimistic concurrency (2011) (11)
- A new pointer-based instruction queue design and its power-performance evaluation (2005) (11)
- A scalable synthetic traffic model of Graph500 for computer networks analysis (2017) (10)
- Efficient cache architectures for reliable hybrid voltage operation using EDC codes (2013) (10)
- On the Scalability of 1- and 2-Dimensional SIMD Extensions for Multimedia Applications (2005) (10)
- Architectural Support for Task Dependence Management with Flexible Software Scheduling (2018) (10)
- Hardware transactional memory with software-defined conflicts (2012) (10)
- An overview of selected hybrid and reconfigurable architectures (2012) (10)
- Global misrouting policies in two-level hierarchical networks (2013) (10)
- Increasing memory bandwidth with wide buses: compiler, hardware and performance trade-offs (1997) (10)
- Carotid-radial pulse wave velocity as a discriminator of intrinsic wall alterations during evaluation of endothelial function by flow-mediated dilatation (2011) (10)
- Breaking the bandwidth wall in chip multiprocessors (2011) (10)
- Efficient Runahead Threads (2010) (10)
- Early 21st Century Processors - Guest Editors' Introduction (2001) (9)
- Hardware Round-Robin Scheduler for Single-ISA Asymmetric Multi-core (2015) (9)
- Reducing Cache Coherence Traffic with a NUMA-Aware Runtime Approach (2018) (9)
- ADAM: an efficient data management mechanism for hybrid high and ultra-low voltage operation caches (2012) (9)
- A Novel Evaluation Methodology to Obtain Fair Measurements in Multithreaded Architectures (2006) (9)
- A low-complexity fetch architecture for high-performance superscalar processors (2004) (9)
- Branch Prediction Using Profile Data (2001) (9)
- Reducing cache coherence traffic with hierarchical directory cache and NUMA-aware runtime scheduling (2016) (9)
- Future Vector Microprocessor Extensions for Data Aggregations (2016) (9)
- A block algorithm for the algebraic path problem and its execution on a systolic array (1988) (9)
- Thread to strand binding of parallel network applications in massive multi-threaded systems (2010) (9)
- Latency tolerant branch predictors (2003) (9)
- PVMC: Programmable Vector Memory Controller (2014) (9)
- Dynamic Cache Partitioning Based on the MLP of Cache Misses (2011) (9)
- A victim cache for vector registers (1997) (9)
- A method for implementation of one-dimensional systolic algorithms with data contraflow using pipelined functional units (1992) (9)
- A Uniform Internal Representation for High-Level and Instruction-Level Transformations (1994) (9)
- Characterizing the Communication Demands of the Graph500 Benchmark on a Commodity Cluster (2014) (8)
- Measuring the performance of multithreaded processors (2007) (8)
- Loop parallelization: revisiting framework of unimodular transformations (1996) (8)
- Throughput Unfairness in Dragonfly Networks under Realistic Traffic Patterns (2015) (8)
- Hierarchical Topologies for Large-scale Two-level Networks (2005) (8)
- Tolerating Branch Predictor Latency on SMT (2003) (8)
- The impact of traffic aggregation on the memory performance of networking applications (2005) (8)
- Systematic Hardware Adaptation Of Systolic Algorithms (1989) (8)
- Quantitative analysis of sequence alignment applications on multiprocessor architectures (2009) (8)
- Analysis of traffic traces for stateful applications (2004) (8)
- Errata on "Measuring Experimental Error in Microprocessor Simulation" (2002) (8)
- A Vector-µSIMD-VLIW Architecture for Multimedia Applications (2005) (8)
- A distributed processor state management architecture for large-window processors (2008) (8)
- On the efficiency of reductions in /spl mu/-SIMD media extensions (2001) (8)
- Optimization of double-loop structures for local networks (1986) (7)
- A Simulation Study of Decoupled Vector Architectures (1999) (7)
- Nebelung: Execution Environment for Transactional OpenMP (2008) (7)
- Bidirectional Scheduling to Minimize Register Requirements (1995) (7)
- EVX: Vector execution on low power EDGE cores (2014) (7)
- Performance Analysis of a New Packet Trace Compressor based on TCP Flow Clustering (2005) (7)
- Selection of the Register File Size and the Resource Allocation Policy on SMT Processors (2008) (7)
- Architecture Performance Prediction Using Evolutionary Artificial Neural Networks (2008) (7)
- AMMC: Advanced Multi-Core Memory Controller (2014) (7)
- Instruction level characterization of the Perfect Club programs on a vector computer (1995) (7)
- Preliminary Analysis of the Cell BE Processor Limitations for Sequence Alignment Applications (2008) (7)
- Hybrid high-performance low-power and ultra-low energy reliable caches (2011) (7)
- Effective usage of vector registers in advanced vector architectures (1997) (7)
- On the maturity of parallel applications for asymmetric multi-core processors (2019) (7)
- BSLD threshold driven power management policy for HPC centers (2010) (7)
- Resource widening versus replication: limits and performance-cost trade-off (1998) (7)
- Cost-Conscious Strategies to Increase Performance of Numerical Programs on Aggressive VLIW Architectures (2001) (7)
- Synchronized access to streams in SIMD vector multiprocessors (1994) (7)
- A General Guide to Applying Machine Learning to Computer Architecture (2018) (7)
- On the selection of adder unit in energy efficient vector processing (2013) (7)
- An Evaluation of Different DLP Alternatives for the Embedded Media Domain (1999) (7)
- Microarchitectural Support for Speculative Register Renaming (2007) (7)
- MAPC: Memory access pattern based controller (2014) (7)
- On the use of systolic algorithms for programming distributed memory multiprocessors (1990) (7)
- Speculative execution for hiding memory latency (2005) (7)
- Automatic Exploration of Potential Parallelism in Sequential Applications (2014) (7)
- Analyzing the Efficiency of L1 Caches for Reliable Hybrid-Voltage Operation Using EDC Codes (2014) (6)
- VIA: A Smart Scratchpad for Vector Units with Application to Sparse Matrix Computations (2021) (6)
- Fair CPU time accounting in CMP+SMT processors (2013) (6)
- Scalability Analysis of Progressive Alignment on a Multicore (2010) (6)
- On the design of hybrid DRAM/SRAM memory schemes for fast packet buffers (2004) (6)
- An MPEG-4 performance study for non-SIMD, general purpose architectures (2003) (6)
- Implicit Transactional Memory in Kilo-Instruction Multiprocessors (2007) (6)
- Physical vs. Physically-Aware Estimation Flow: Case Study of Design Space Exploration of Adders (2014) (6)
- Implicit vs. explicit resource allocation in SMT processors (2004) (6)
- HPC System Software for Regular and Irregular Parallel Applications (2013) (6)
- On the Problem of Evaluating the Performance of Multiprogrammed Workloads (2010) (6)
- DReAM: Per-Task DRAM Energy Metering in Multicore Systems (2014) (6)
- A complexity-effective simultaneous multithreading architecture (2005) (6)
- Profiling and Optimizing Transactional Memory Applications (2012) (6)
- Profiling Transactional Memory applications on an atomic block basis : A Haskell case study (2009) (6)
- From Plasma to BeeFarm: Design Experience of an FPGA-Based Multicore Prototype (2011) (6)
- Branch Classification for SMT Fetch Gating (2002) (6)
- Levels and rates of change in carotid-radial pulse wave velocity associated with reactive hyperaemia: Analysis of the dependence on transient ischemia length (2010) (6)
- A conflict-free memory banking architecture for fast VOQ packet buffers (2003) (6)
- An Integrated Vector-Scalar Design on an In-Order ARM Core (2017) (5)
- Adaptive and application dependent runtime guided hardware prefetcher reconfiguration on the IBM POWER7 (2015) (5)
- Load balancing using dynamic cache allocation (2010) (5)
- PARSECSs (2015) (5)
- CDE : A Compiler-driven , Dependence-Centric , Eager-executing Architecture for the Billion Transistors Era (2003) (5)
- LPA: A First Approach to the Loop Processor Architecture (2008) (5)
- Hybrid/Heterogeneous Programming with OMPSS and Its Software/Hardware Implications (2017) (5)
- On the Problem of Minimizing Workload Execution Time in SMT Processors (2007) (5)
- A Simple Low-Energy Instruction Wakeup Mechanism (2003) (5)
- Graph partitioning applied to DAG scheduling to reduce NUMA effects (2018) (5)
- Scalable multicore architectures for long DNA sequence comparison (2011) (5)
- DeTrans: Deterministic and Parallel execution of Transactions (2014) (5)
- Per-task Energy Accounting in Computing Systems (2014) (5)
- A novel renaming mechanism that boosts software prefetching (2001) (5)
- Hardware Transactional Memory with Operating System Support, HTMOS (2007) (5)
- Vectorized AES Core for High-throughput Secure Environments (2008) (5)
- Branch classification to control instruction fetch in simultaneous multithreaded architectures (2002) (5)
- Network unfairness in dragonfly topologies (2016) (5)
- Looking for Novel Ways to Obtain Fair Measurements in Multithreaded Architectures (2006) (5)
- Initial Results on Fuzzy Floating Point Computation for Multimedia Processors (2002) (5)
- Early 21 st Century Processors (2001) (5)
- TagTM - accelerating STMs with hardware tags for fast meta-data access (2012) (5)
- SMT Malleability in IBM POWER5 and POWER6 Processors (2013) (5)
- Proceedings of the 9th international conference on Supercomputing (1995) (5)
- FaulTM-multi : Fault Tolerance for Multithreaded Applications Running on Transactional Memory Hardware (2011) (5)
- Circuit design of a dual-versioning L1 data cache (2012) (5)
- Trends and techniques for energy efficient architectures (2010) (5)
- Better branch prediction through prophet/critic hybrids (2005) (5)
- Improving Predication Efficiency through Compaction/Restoration of SIMD Instructions (2020) (5)
- To Distribute or Not to Distribute: The Question of Load Balancing for Performance or Energy (2017) (5)
- Compile time support for using Transactional Memory in C / C + + applications (5)
- Comparing last-level cache designs for CMP architectures (2010) (5)
- Evolutionary system for prediction and optimization of hardware architecture performance (2008) (4)
- TMbox: A Flexible and Reconfigurable 16-Core Hybrid Transactional Memory System (2011) (4)
- An Abstraction Methodology for the Evaluation of Multi-core Multi-threaded Architectures (2011) (4)
- Profile-guided transaction coalescing—lowering transactional overheads by merging transactions (2013) (4)
- On the Performance of Fetch Engines Running DSS Workloads (2000) (4)
- Control-flow independence reuse via dynamic vectorization (2005) (4)
- Feasibility of QoS for SMT (2004) (4)
- Scalable Distributed Register File (2004) (4)
- Workload Characterization of Stateful Networking Applications (2005) (4)
- Novel SRAM bias control circuits for a low power L1 data cache (2012) (4)
- Soft Real-Time Scheduling on SMT Processors with Explicit Resource Allocation (2008) (4)
- On the Effectiveness of XOR-Mapping Schemes for Cache Memories (1996) (4)
- HPCS 2013 panel: The era of exascale sciences: Challenges, needs and requirements (2013) (4)
- An Optimized Front-End Physical Register File with Banking and Writeback Filtering (2004) (4)
- A survey of dual data cache systems (2012) (4)
- A Vulnerability Factor for ECC-protected Memory (2019) (4)
- Exploiting Instruction and Data Level Parallelism in Future High Performance Processors (1997) (4)
- Tareador: The Unbearable Lightness of Exploring Parallelism (2015) (4)
- A Comparative Study of Redundancy in Trace Caches (Research Note) (2002) (4)
- Impact on performance of fused multiply-add units in aggressive VLIW architectures (1999) (4)
- Exploiting intra-task slack time of load operations for DVFS in hard real-time multi-core systems (2011) (4)
- Systematic design of two-level pipelined systolic arrays with data contraflow (1988) (4)
- An Academic RISC-V Silicon Implementation Based on Open-Source Components (2020) (4)
- Hybrid Transactional Memory with Pessimistic Concurrency Control (2011) (4)
- Conflict-Free Strides for Vectors in Matched Memories (1991) (3)
- Initial Evaluation of Multimedia Extensions on VLIW Architectures (2004) (3)
- Speculative early register release (2006) (3)
- TM-dietlibc: A TM-aware Real-World System Library (2013) (3)
- Exploiting Execution Locality with a Decoupled Kilo-Instruction Processor (2005) (3)
- Runtime-Assisted Shared Cache Insertion Policies Based on Re-reference Intervals (2017) (3)
- Dynamic memory interval test vs. interprocedural pointer analysis in multimedia applications (2005) (3)
- Automatic generation of loop scheduling for VLIW (1995) (3)
- Instruction fetch architectures and code layout optimizations (2001) (3)
- Evaluating kilo-instruction multiprocessors (2004) (3)
- Effective instruction prefetching via fetch prestaging (2005) (3)
- DReAM: An Approach to Estimate per-Task DRAM Energy in Multicore Systems (2016) (3)
- QuakeTM : Parallelizing a Complex Serial Application Using Transactional Memory (2008) (3)
- PAMS: Pattern Aware Memory System for embedded systems (2014) (3)
- APMC: advanced pattern based memory controller (abstract only) (2014) (3)
- Characterizing Power and Temperature Behavior of POWER6-Based System (2011) (3)
- Simulation environment for studying overlap of communication and computation (2010) (3)
- Reducing fetch architecture complexity using procedure inlining (2004) (3)
- Dynamic transaction coalescing (2014) (3)
- A Deep Learning Mapper (DLM) for Scheduling on Heterogeneous Systems (2017) (3)
- Analysis and simulation of multiplexed single-bus networks with and without buffering (1985) (3)
- Implementation of systolic algorithms using pipelined functional units (1990) (3)
- The Ultimate DataFlow for Ultimate SuperComputers-on-a-Chip, for Scientific Computing, Geo Physics, Complex Mathematics, and Information Processing (2020) (3)
- Quantifying the benefits of SPECint distant parallelism in simultaneous multithreading architectures (1999) (3)
- RICH (2020) (3)
- A european perspective on supercomputing (2009) (3)
- On the Efficiency of Reductions in µ-SIMD Media Extensions (2001) (3)
- A performance study of out-of-order vector architectures and short registers (1998) (3)
- International Conference on Parallel Architectures and Compilation Techniques, PACT '12, Minneapolis, MN, USA - September 19 - 23, 2012 (2012) (3)
- Asynchronous and Exact Forward Recovery for Detected Errors in Iterative Solvers (2018) (3)
- Runtime-Assisted Cache Coherence Deactivation in Task Parallel Programs (2018) (3)
- Optimizing computation-communication overlap in asynchronous task-based programs: poster (2019) (3)
- A case for merging the ILP and DLP paradigms (1998) (3)
- Cost effective memory disambiguation for multimedia codes (2002) (3)
- Effective usage of vector registers in decoupled vector architectures (1998) (3)
- Branch predictor guided instruction decoding (2006) (3)
- Temporal pattern of pulse wave velocity during brachial hyperemia reactivity (2011) (3)
- Conflict-free access to streams in multiprocessor systems (1993) (3)
- On-the-fly adaptive routing for dragonfly interconnection networks (2015) (2)
- Semi-automatic validation of cycle-accurate simulation infrastructures: The case for gem5-x86 (2020) (2)
- Maintaining Thousands of In-flight Instructions (2004) (2)
- Multiple Stream Prediction (2005) (2)
- A Fully Parameterizable Low Power Design of Vector Fused Multiply-Add Using Active Clock-Gating Techniques (2016) (2)
- Guest Editorial: Special Issue on Network and Parallel Computing for Emerging Architectures and Applications (2019) (2)
- LU-decomposition on a linear systolic array processor (1989) (2)
- Approaching a Smart Sharing of Resources in SMT Processors (2004) (2)
- Feasibility of QoS for SMT by Resource Allocation (2)
- The Impact of Application's Micro-Imbalance on the Communication-Computation Overlap (2011) (2)
- Software Trace Cache for Commercial Applications (2002) (2)
- POSTER: Exploiting asymmetric multi-core processors with flexible system software (2016) (2)
- A Stream Processor Front-end (2000) (2)
- The Ultimate Data Flow for Ultimate Super Computers-on-a-Chip (2021) (2)
- Using Dynamic Runtime Testing for Rapid Development of Architectural Simulators (2014) (2)
- Exact and approximate models for multiprocessors with single bus and distributed memory (1986) (2)
- Joint Circuit-System Design Space Exploration of Multiplier Unit Structure for Energy-Efficient Vector Processors (2015) (2)
- Runtime Aware Architectures (2015) (2)
- The Performance of Decoupled Architectures1 (1996) (2)
- Parallel architecture and compilation techniques: selection of workshop papers, guests' editors introduction (2001) (2)
- Enabling SMT for real-time embedded systems (2004) (2)
- Trace filtering of multithreaded applications for CMP memory simulation (2013) (2)
- A block algorithm and optimal fixed-size systolic array processor for the algebraic path problem (1989) (2)
- Imposing coarse-grained reconfiguration to general purpose processors (2015) (2)
- Kilo-instruction processors, runahead and prefetching (2006) (2)
- Hypernode Reduction Modulo Scheduling 1 (1995) (2)
- Hybrid Parallel Programming with MPI/StarSs (2011) (2)
- Identifying Critical Code Sections in Dataflow Programming Models (2013) (2)
- Efficiency analysis of modern vector architectures: vector ALU sizes, core counts and clock frequencies (2019) (2)
- FlexVC: Flexible Virtual Channel Management in Low-Diameter Networks (2017) (2)
- Architectures for one billion of transistors (2000) (2)
- Performance and energy effects on task-based parallelized applications (2018) (2)
- iQ: An Efficient and Flexible Queue-Based Simulation Framework (2017) (2)
- Vector Processing-Aware Advanced Clock-Gating Techniques for Low-Power Fused Multiply-Add (2018) (2)
- Using Hardware Resource Allocation to Balance HPC Applications (2010) (2)
- Mechanical properties of the aortic arterial wall during 24 hours: a preliminary study in conscious sheep (2011) (2)
- Memory Access Synchronization in Vector Multiprocessors (1994) (2)
- Advances in the Hierarchical Emergent Behaviors (HEB) Approach to Autonomous Vehicles (2020) (1)
- Reimagining Heterogeneous Computing: A Functional Instruction-Set Architecture Computing Model (2015) (1)
- Dynamic Memory Instruction Bypassing (2003) (1)
- Chip Multiprocessors with Implicit Transactions (2006) (1)
- The Network Adapter: The Missing Link between MPI Applications and Network Performance (2012) (1)
- Vitruvius+: An Area-Efficient RISC-V Decoupled Vector Coprocessor for High Performance Computing Applications (2022) (1)
- Hardware / Software Techniques for Assisted Execution Runtime Systems (2012) (1)
- Registers Size Influence on Vector Architectures (1998) (1)
- Enhancing the performance of assisted execution runtime systems through hardware/software techniques (2012) (1)
- SIMULATION OF THE ARTERIAL ELASTICITY INFLUENCE ON THE AMBULATORY ARTERIAL STIFFNESS INDEX AASI (2009) (1)
- Future ILP processors (2004) (1)
- Synchronized Access To Streams In Multiprocessors (1993) (1)
- Hybrid Cache Designs for Reliable Hybrid High and Ultra-Low Voltage Operation (2014) (1)
- Multicore: The View from Europe (2010) (1)
- Proceedings of the Second Conference on Computing Frontiers, 2005, Ischia, Italy, May 4-6, 2005 (2005) (1)
- Exploiting the Dependency Checking Logic of the Rename Stage for Soft Error Detection (2009) (1)
- Big Data Processing: Data Flow vs Control Flow (New Benchmarking Methodology) (2014) (1)
- Mapping QR decomposition of a banded matrix on a ID systolic array with data contraflow and pipelined functional units (1992) (1)
- Performance and energy effects on task-based parallelized applications User-directed versus manual vectorization (2018) (1)
- Power-efficient VLIW design using clustering and widening (2008) (1)
- Kernel-to-User-Mode Transition-Aware Hardware Scheduling (2015) (1)
- Efficiency analysis of modern vector architectures: vector ALU sizes, core counts and clock frequencies (2019) (1)
- Rapid Development of Error-Free Architectural Simulators Using Dynamic Runtime Testing (2011) (1)
- Revisiting Framework of Linear Loop Transformations to Extract Full Loop Parallelism (1995) (1)
- Vallejo-Hybrid Transactional Memory with Pessimistic Concurrency Control Hybrid Transactional Memory with Pessimistic Concurrency Control 1 (2014) (1)
- High-performance and low-power VLIW cores for numerical computations (2004) (1)
- Dynamic-vector execution on a general purpose EDGE chip multiprocessor (2014) (1)
- Sensible Energy Accounting with Abstract Metering for Multicore Systems (2015) (1)
- Red blue traces: Trace cache redundancy (1999) (1)
- Studying New Ways for Improving Adaptive History Length Branch Predictors (2009) (1)
- Power-Performance Trade-Offs in Wide and Clustered VLIW Cores for Numerical Codes (2003) (1)
- Architecture and Code Optimization (2011) (1)
- A case for resource-conscious out-of-order processors: towards kilo-instruction in-flight processors (2003) (1)
- When Sally Met Harry or When AI Met HPC (2021) (1)
- A latency-conscious SMT branch prediction architecture (2004) (1)
- Access to streams in multiprocessor systems (1993) (1)
- A Cost-Effective Architecture for Vectorizable Numerical and Multimedia Applications (2003) (1)
- On Automatic Loop Data-Mapping for Distributed-Memory Multiprocessors (1991) (1)
- High performance computing : Third International Symposium, ISHPC 2000, Tokyo, Japan, October 16-18, 2000 : proceedings (2000) (1)
- KIMP: Multicheckpointing Multiprocessors (2005) (1)
- Instructions-Wake-Up Mechanisms: Power and Timing Evaluation (2004) (1)
- Merging ILP and DLP for High Performance (1997) (1)
- Runtime-Guided ECC Protection using Online Estimation of Memory Vulnerability (2020) (1)
- Determinism at Standard-Library Level in TM-Based Applications (2017) (1)
- Resource-bounded multicore emulation using Beefarm (2012) (1)
- Picos, A Hardware Task-Dependence Manager for Task-Based Dataflow Programming Models (2017) (1)
- A Study of Data Sets and Affinity in the Perfect Club (1993) (1)
- Revisiting Framework of Linear Loop Transformation (1995) (1)
- A partitioned instruction queue to reduce instruction wakeup energy (2004) (1)
- SEDEA: A Sensible Approach to Account DRAM Energy in Multicore Systems (2017) (0)
- 2 Prior Work in Dynamic Cache Partitioning Stack Distance Histogram (2007) (0)
- Proceedings of the International Conference on Application Specific Array Processors, September 2-4, 1991, Barcelona, Spain (1991) (0)
- Edinburgh Research Explorer Multiple-banked Register File Architectures (2018) (0)
- Proceedings of the 2001 International Conference on Parallel Processing, ICPP 2002, 3-7 September 2001, Valencia, Spain (2001) (0)
- POSTER: An integrated vector-scalar design on an in-order ARM core (2016) (0)
- A systolic algorithm for the fast computation of the connected components of a graph (1988) (0)
- Code Semantic-Aware Runahead Threads (2009) (0)
- The Dual Data Cache: Improving Vector Caching in Scalar Processors (1994) (0)
- Mu It iple-Ban ked Register File Architectures (2000) (0)
- Energy saving through a simple load control mechanism (2007) (0)
- HwA 1 : REDUCED MEMORY LATENCY FOR REGULAR DATA ACCESS (2007) (0)
- A cost effective architecture for vectorizable numerical and multimedia applications (2001) (0)
- Message from the Program Chair (2006) (0)
- DReAM (2016) (0)
- EazyHTM (2009) (0)
- Performance and Power Evaluation of Clustered VLIW Processors with Wide Functional Units (2004) (0)
- The Ultimate DataFlow for Ultimate SuperComputers-on-a-Chips (2020) (0)
- DVINO: A RISC-V Vector Processor Implemented in 65nm Technology (2022) (0)
- Limits on Early Release of Physical Registers (0)
- VAQUERO: A Scratchpad-based Vector Accelerator for Query Processing (2023) (0)
- Proceedings, International Conference on Parallel Processing, 3-7 September 2001, Valencia, Spain (2001) (0)
- Performance and Energy Efficient Hardware-Based Scheduler for Symmetric/Asymmetric CMPs (2015) (0)
- DIA: A Complexity-Effective Decoding Architecture (2009) (0)
- Analyzing reference patterns in automatic data distribution tools (1995) (0)
- Percutaneous closure of aortic pseudoaneurysm Cierre percutáneo de seudoaneurisma aórtico (2021) (0)
- Network Synchronization and Out-of-Order Access to Vectors (1994) (0)
- Decoupled State-Execute Architecture (2005) (0)
- Evaluación del rendimiento paralelo en el nivel macro bloque del decodificador H.264 en una arquitectura multiprocesador cc-NUMA (2009) (0)
- Core to Memory Interconnection Implications for Forthcoming On-Chip Multiprocessors (2007) (0)
- CURRENT ISSUE NEWS BLOGS OPINION RESEARCH PRACTICE CAREERS MAGAZINE ARCHIVE (2013) (0)
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- Different approaches using Kilo-instruction Processors (2005) (0)
- PrioRAT: Criticality-Driven Prioritization Inside the On-Chip Memory Hierarchy (2021) (0)
- Automatic data-mapping for distributed-memory multiprocessor systems (1993) (0)
- Quantifying the Benefits of SPECint Distant Parallelism in Simultaneous Multi-Threading Architectures (1999) (0)
- hdSMT : An Heterogeneity-Aware Simultaneous Multithreading Architecture (2005) (0)
- Session 1: Phase Behavior (2005) (0)
- Analysis of a High Performance DRAM/SRAM Memory Scheme for Fast Packet Buffers (0)
- Using Dynamic Runtime Testing for Rapid Development of Architectural Simulators (2012) (0)
- HwA 2 : SPECIAL MEMORY INTERLEAVING SCHEMES (2007) (0)
- Bubble Flow Control in High-Radix Hierarchical Networks (2012) (0)
- On-the-fly adaptive routing for dragonfly interconnection networks (2014) (0)
- Balanced Loop Partitioning Using GTS (1991) (0)
- Workshop 20 introduction: Workshop on multithreaded architectures and applications - MTAAP’08 (2008) (0)
- Memory Vulnerability: A Case for Delaying Error Reporting (2018) (0)
- High Performance Computing - HiPC 2002: 9th International Conference Bangalore, India, December 18-21, 2002, Proceedings (2002) (0)
- Contention-based Nonminimal Adaptive Routing in (2015) (0)
- The Problem of Evaluating CPU-GPU Systems with 3D Visualization Applications (2012) (0)
- Chairmen's introduction (1993) (0)
- A Case for Energy-Aware Accounting in Large-Scale Computing Facilities Cost Metrics and Implications for Processor Design (2010) (0)
- The Mont-Blanc Prototype (2019) (0)
- Hierarchical Gaussian Topologies (2005) (0)
- Extending the Flexibility of ACMPs for Mobile Devices Using Alternative Cache Configurations (2017) (0)
- RICH: implementing reductions in the cache hierarchy (2020) (0)
- Session details: Special session on memory wall (2004) (0)
- BSC Vision Towards Exascale (2009) (0)
- Killer-mobiles - The Way Towards Energy Efficient High Performance Computers? (2013) (0)
- Instruction-Level Parallelism and Uniprocessor Architecture - Introduction (1999) (0)
- The computer architecture arena faces exciting challenges as it attempts to meet the design goals and constraints that new markets , changing applications , and fast-moving semiconductor technology impose (2001) (0)
- Turbocharging boosted transactions or: how i learnt to stop worrying and love longer transactions (2009) (0)
- Author retrospective for software trace cache (2014) (0)
- A Brief Overview on Runtime-Aware Architectures (2015) (0)
- Efficient Execution of Mixed Application Workloads in a Hard Real-Time Multicore System (2009) (0)
- Supercomputing for the Future, Supercomputing from the Past (Keynote) (2008) (0)
- Guest Editorial: Special Issue on Network and Parallel Computing for Emerging Architectures and Applications (2019) (0)
- Introducing Runahead Threads for SMT Processors (2007) (0)
- Investigating the Predictability of Linked Data Structures. (2002) (0)
- Parallelization Strategies for Smith Waterman Algorithm on CellBE Friman (2008) (0)
- Editorial (1991) (0)
- A simple speculative load control mechanism for energy saving (2006) (0)
- High Performance Computing (2019) (0)
- Profiling and Optimizing Transactional Memory Applications (2011) (0)
- RMS-TM: a comprehensive benchmark suite for transactional memory systems (abstracts only) (2011) (0)
- Runtime Aware Architectures; Barcelona Supercomputing Center at a glance (2015) (0)
- POSTER: An Optimized Predication Execution for SIMD Extensions (2019) (0)
- A Complexity-Effective Decoding Architecture Based on Instruction Streams (2004) (0)
- 19 Balanced Loop Partitioning Using GTS (0)
- Reducing Simulation Time (2006) (0)
- Increasing performance with multiply-add units and wide buses (2007) (0)
- Access To Vectors In Multi-module Memories (1994) (0)
- MFLUSH: Handling Long-Latency Loads in SMT On-Chip Multiprocessors (2008) (0)
- Parallel Processing in Sequence Matching (2005) (0)
- Performance and energy effects on task-based parallelized applications (2018) (0)
- A Comprehensive Description of Kilo-Instruction Processors (2004) (0)
- Centre de Computació i Comunicacions de Catalunya (C4) (1996) (0)
- Using Arm’s scalable vector extension on stencil codes (2019) (0)
- Runahead Threads: Reducing Resource Contention in SMT Processors (2007) (0)
- Appears in the “ XVI Jornadas de Paralelismo ” . Granada , Spain , September 2005 KIMP : Multicheckpointing Multiprocessors (2005) (0)
- Network unfairness in dragonfly topologies (2016) (0)
- Hardware support for early register release (2005) (0)
- Determinism at Standard-Library Level in TM-Based Applications (2015) (0)
- The international race towards Exascale in Europe (2019) (0)
- ENDOTHELIAL FUNCTION EVALUATED BY MEANS OF CHANGES IN CAROTID- RADIAL PULSE WAVE VELOCITY ASSOCIATED WITH REACTIVE HYPERAEMIA: DEPENDENCE ON THE BASAL VELOCITY LEVELS AND ON THE TRANSIENT ISCHEMIA LENGTH: PP.21.168 (2011) (0)
- Proceedings of the 25th Annual International Symposium on Computer Architecture, ISCA 1998, Barcelona, Spain, June 27 - July 1, 1998 (1998) (0)
- Performance Advantages Of Merging Instruction- And Data-Level Parallelism (1998) (0)
- Proceedings of the 7th International Conference on High Performance Computing (2000) (0)
- Software trace cache (1999) (0)
- Registers Size Innuence on Vector Architectures (2007) (0)
- IMMEDIATE, BUT NOT LATER OR MAXIMAL, CHANGES IN CAROTID-RADIAL PULSE WAVE VELOCITY ASSOCIATED WITH REACTIVE HYPERAEMIA DEPEND ON THE OCCLUSION LENGTH: PP.10.414 (2010) (0)
- Runtime-aware Architectures : A Second Approach (2015) (0)
- Welcome to the Barcelona Supercomputing Center - The National Supercomputing Center (BSC-CNS) website. (2016) (0)
- Topic 15+20: Multimedia and Embedded Systems (2001) (0)
- Festa de final de curs amb famílies (2017) (0)
- Determinism at Standard Library Level in Transactional Memory Based Applications (2015) (0)
- Exploiting Inactive Rename Slots for Detecting Soft Errors (2010) (0)
- A Flexible Hybrid Transactional Memory Multicore on FPGA (2011) (0)
- Percutaneous closure of aortic pseudoaneurysm (2020) (0)
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